Pamela S Hempstead, Age 756327 106Th St SE, Clear Lake, MN 55319

8219776, Jul 10, 2012

Dec 21, 2009

12/643471

Carl Forhan - Rochester MN, US
Pamela Hempstead - Oronoco MN, US
Michael Hicken - Rochester MN, US
Randy Reiter - Rochester MN, US
Timothy Swatosh - Rochester MN, US

LSI Corporation - Milpitas CA

G06F 12/00

711202, 711103, 711170, 711171, 711203, 711206, 711207, 711208, 711209, 36518533

Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

8301861, Oct 30, 2012

Apr 29, 2010

12/769910

Randy Reiter - Rochester MN, US
Timothy Swatosh - Rochester MN, US
Pamela Hempstead - Oronoco MN, US
Michael Hicken - Rochester MN, US

LSi Corporation - Milpitas CA

G06F 12/06

711170, 711202, 711E12078

Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.

8352690, Jan 8, 2013

Mar 24, 2010

12/730627

Carl Forhan - Rochester MN, US
Timothy Swatosh - Rochester MN, US
Pamela Hempstead - Oronoco MN, US
Timothy Lund - Rochester MN, US
Michael Hicken - Rochester MN, US

LSI Corporation - Milpitas CA

G06F 12/02
G06F 12/00

711156, 711103

Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present.

8645618, Feb 4, 2014

Dec 21, 2011

13/332849

Vinay Ashok Somanache - Pune-Maharashtra, IN
Jackson L. Ellis - Fort Collins CO, US
Michael S. Hicken - Rochester MN, US
Timothy W. Swatosh - Rochester MN, US
Martin S. Dell - Bethlehem PA, US
Pamela S. Hempstead - Oronoco MN, US

LSI Corporation - San Jose CA

G06F 12/00

711103

A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context.

2011002, Jan 27, 2011

Jul 24, 2009

12/508915

Tim Lund - Rochester MN, US
Carl Forhan - Rochester MN, US
Timothy Swatosh - Rochester MN, US
Pamela Hempstead - Oronoco MN, US
Michael Hicken - Rochester MN, US
Bryan Holty - Rochester MN, US
John Paradise - Rochester MN, US

G06F 12/00
G06F 12/02

711103, 711170, 711E12001, 711E12008

Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory.

2011007, Mar 24, 2011

Apr 29, 2010

12/769882

Randy Reiter - Rochester MN, US
Timothy Swatosh - Rochester MN, US
Pamela Hempstead - Oronoco MN, US
Michael Hicken - Rochester MN, US

G06F 12/00
G06F 12/02
G06F 12/08
G06F 12/10

711103, 711206, 711126, 711E12001, 711E12008, 711E12059, 711E1202

Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache.

2013001, Jan 17, 2013

Dec 22, 2011

13/334599

Vinay Ashok Somanache - Pune-Maharashtra, IN
Michael S. Hicken - Rochester MN, US
Pamela S. Hempstead - Oronoco MN, US
Timothy W. Swatosh - Rochester MN, US
Jackson L. Ellis - Fort Collins CO, US
Martin S. Dell - Bethlehem PA, US

G06F 12/02

711103, 711E12008

A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context.

2013001, Jan 17, 2013

Jan 5, 2012

13/344030

Vinay Ashok Somanache - Aundh Annexe, IN
Jackson L. Ellis - Fort Collins CO, US
Pamela S. Hempstead - Oronoco MN, US
Timothy W. Swatosh - Rochester MN, US
Michael S. Hicken - Rochester MN, US
Martin S. Dell - Bethlehem PA, US

G06F 12/00

711103, 711E12008

An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to maintain die-based information used for operation of a flash lane controller (FLC). The second circuit may be configured to manage contexts that are actively being processed by the flash lane controller (FLC). The third circuit may be configured to perform pipeline execution of a plurality of the contexts managed by the second circuit.