Peter T Chow, Age 541161 Johnson Ave, San Jose, CA 95129

Peter Chow Phones & Addresses

1161 Johnson Ave, San Jose, CA 95129 (408) 255-7360

Middleburg, FL

Green Cove Springs, FL

Whitehall, MI

Santa Clara, CA

Cupertino, CA

1161 Johnson Ave, San Jose, CA 95129 (408) 674-2615

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Work

Position: Professional/Technical

Mentions for Peter T Chow

Career records & work history

Medicine Doctors

Peter Chow Photo 1

Peter Michael W C Chow

Specialties:
Anesthesiology
Education:
Institute Of Medicine I (1972)

Publications & IP owners

Us Patents

Integrated Multiport Switch Having Shared Data Receive Fifo Structure

US Patent:
6393021, May 21, 2002
Filed:
Dec 18, 1997
Appl. No.:
08/992815
Inventors:
Peter Ka-Fai Chow - San Jose CA
Thomas J. Runaldue - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04Q 1100
US Classification:
370378, 370381, 370428, 370463, 711100
Abstract:
An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM. When the accumulated data for a given port is to be written to the RAM in a subsequent write cycle, it is then combined with additional incoming data for the same port received at that time for transfer to the RAM.

Apparatus And Method For Modifying A Limit Of A Retry Counter In A Network Switch Port In Response To Exerting Backpressure

US Patent:
6563790, May 13, 2003
Filed:
May 21, 1999
Appl. No.:
09/316185
Inventors:
Ching Yu - Santa Clara CA
Bahadir Erimli - Campbell CA
Jenny Liu Fischer - Mountain View CA
Peter Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3108
US Classification:
370230, 370235
Abstract:
A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter for counting data packet transmission attempts within any one of the respective switch ports if backpressure is asserted by that port. A retry limit value for the retry counter is modified to ensure that the total number of retrys does not exceed a maximum total number of allowable retrys. The resetting of the retry counter within a port after assertion of backpressure affords the port a greater probability of transmitting earlier under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch. The modification of the retry limit value ensures that the number of retrys for the port does not exceed industry standards.

Apparatus And Method For Validating And Updating An Ip Checksum In A Network Switching System

US Patent:
6571291, May 27, 2003
Filed:
May 1, 2000
Appl. No.:
09/562287
Inventors:
Peter Ka-Fai Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1516
US Classification:
709230, 709236, 370392, 370389
Abstract:
A network switching system configured for evaluating an incoming data packet including layer 3 information having an Internet Protocol (IP) header and an IP checksum. The system includes a buffer memory and network switch. The network switch includes a media access control (MAC) module having a receive data portion and a transmit data portion. The receive data portion is configured to extract the IP checksum from the IP header and to validate the IP checksum. A queue block is configured to send the IP checksum to the buffer memory for storage therein. A layer 3 internal rules checker is configured to receive layer 3 information and to modify the IP header based on a field of the IP header. The internal rules checker generates an identifier indicating the field needs to be changed. The network switch also includes a dequeue block configured to receive the identifier and to retrieve the IP checksum from the buffer memory and to incrementally update the IP checksum as a result of the change to the field, with the updated IP checksum being received by the transmit data portion of the MAC module.

Apparatus And Method For Specifying Successive Byte Locations For Evaluating Data Packets In A Network Switch Port

US Patent:
6678276, Jan 13, 2004
Filed:
Jun 15, 2000
Appl. No.:
09/594608
Inventors:
Shr-Jie Tzeng - Fremont CA
Peter Ka-Fai Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04L 1256
US Classification:
3703957, 370423
Abstract:
A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802. 3) network without blocking of incoming data packets, includes a plurality of ports. Each port is configured to compare a corresponding incoming data packet with at least one template. Each template has min terms specifying a corresponding prescribed value that is to be compared with a corresponding selected byte of the incoming data packet by the port. The network switch also includes a manager module configured to supply a next location field to the corresponding port. The corresponding port determines a next corresponding selected byte of the incoming data packet from the next location field for a next comparison with a next corresponding prescribed value in response to a next location field request. As a result, a port may jump directly to the next relevant byte location after finishing a current evaluation of a current byte location in a received data packet, bypassing non-relevant bytes preceding the next relevant byte.

Apparatus And Method For Efficient Evaluation Of Equations Which Generate Frame Tags In A Network Switch

US Patent:
6693908, Feb 17, 2004
Filed:
May 1, 2000
Appl. No.:
09/562290
Inventors:
Shr-jie Tzeng - Fremont CA
Peter Ka-Fai Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04L 1256
US Classification:
370392, 370389
Abstract:
A network switch, configured for performing layer and layer switching in an Ethernet (IEEE 802. 3) network includes a network switch port having a filter configured for evaluating an incoming data packet. The filter includes a min term memory configured or storing min term values. Each min term value is stored based on a location of a corresponding selected byte of the incoming data packet for comparison, an expression portion specifying a corresponding comparison operation, and a template identifier field that specifies templates that use the corresponding min term. The template identifier field includes an equation identifier and an obsolete equation identifier. A header memory is configured for storing an effect min term and a plurality of equation identifiers. The effect min term specifies which min terms are necessary for comparison. A min term generator is configured for simultaneously comparing a received byte of the incoming data packet with the necessary min terms that correspond to the received byte and generates respective min term comparison results.

Apparatus And Method For Storing Min Terms In A Central Min Term Memory For Efficient Sharing By A Plurality Of Network Switch Ports

US Patent:
6714542, Mar 30, 2004
Filed:
May 1, 2000
Appl. No.:
09/562291
Inventors:
Shr-jie Tzeng - Fremont CA
Peter Ka-Fai Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04L 1256
US Classification:
370392, 370389, 370400
Abstract:
A network switch, configured for performing layer and layer switching in an Ethernet (IEEE 802. 3) network without blocking of incoming data packets, includes a plurality of network switch ports each having a filter (i. e. , a packet classifier module) configured for evaluating an incoming data packet on an instantaneous basis. The filter performs simultaneous comparisons between the incoming data stream of the data packet and multiple templates configured for identifying respective data protocols, enabling the network switch to perform layer switching for 100 Mbps and gigabit networks without blocking in the network switch. Each template is composed of a plurality of min terms, wherein each min term specifies a prescribed comparison operation within a selected data byte of the incoming data packet. The templates may be programmed by a user and stored in a central min term memory separate from each network switch port. A min term controller controls the fetching of min terms from the min term memory eliminating the need to store all min terms at each network switch port.

System And Method For Network Management Of Local Area Networks Having Non-Blocking Network Switches Configured For Switching Data Packets Between Subnetworks Based On Management Policies

US Patent:
6718379, Apr 6, 2004
Filed:
Jun 9, 2000
Appl. No.:
09/590685
Inventors:
Gopal S. Krishna - San Jose CA
Peter Ka-Fai Chow - San Jose CA
Somnath Viswanath - San Jose CA
Shr-Jie Tzeng - Fremont CA
Mrudula Kanuri - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 15173
US Classification:
709223, 709220, 709238
Abstract:
A centralized policy server sends policy messages, that describe network management policy, to network switches. Each policy message includes a packet attribute that enables a network switch to uniquely identify a received data packet, and either a priority level or network switch action that describes the switching operation to be performed by the network switch. The network switches are configured for implementing the network management policy by storing switching actions for prescribed data packets, and templates that specify frame data parameters for identifying the prescribed data packets. Each network switch, configured for performing layer and layer switching in an Ethernet (IEEE 802. 3) network without blocking of incoming data packets, includes in each network switch port a packet classifier module configured for classifying a received data packet based on a template generated based on the policy messages. In particular, the network switch stores a plurality of user-programmable templates, each configured for identifying a corresponding class of data packet.

Apparatus And Method For Programmably Modifying A Limit Of A Retry Counter In A Network Switch Port In Response To Exerting Backpressure

US Patent:
6725270, Apr 20, 2004
Filed:
May 21, 1999
Appl. No.:
09/316184
Inventors:
Ching Yu - Santa Clara CA
Bahadir Erimli - Campbell CA
Jenny Liu Fischer - Mountain View CA
Peter Chow - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1516
US Classification:
709229, 370230
Abstract:
A network switch having switch ports for communication of data packets with respective computer network nodes according to CSMA/CD protocol that resets a retry counter for counting data packet transmission attempts within any one of the respective switch ports if backpressure is asserted by that port. A retry limit value for the retry counter is selectively modified according to programmed information to ensure that the total number of retrys does not exceed a maximum total number of allowable retrys. Resetting the retry counter within a port after assertion of backpressure affords the port a greater probability of transmitting earlier under the CSMA/CD protocol, thus more quickly relieving congestion which may occur in the network switch. Selective modification of the retry limit value according to programmed information adds flexibility to vary the maximum total number of allowable retrys based upon current network switch conditions or the priority of a particular data packet.

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