Philip Douglas Crary, Age 62Kansas City, MO
Philip Crary Phones & Addresses
Lake Waukomis, MO
Torrance, CA
26061 Calle Cresta, Mission Viejo, CA 92692
Alexandria, VA
Bellefonte, PA
State College, PA
Mentions for Philip Douglas Crary
Publications & IP owners
Us Patents
Fft Based Acquisition Techniques For Satellite Based Navigation Systems
US Patent:
8384592, Feb 26, 2013
Filed:
Sep 30, 2009
Appl. No.:
12/570942
Inventors:
Philip Crary - Mission Viejo CA, US
Qinfang Sun - Cupertino CA, US
Qinfang Sun - Cupertino CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G01S 19/30
G01S 19/24
G01S 19/37
G01S 19/24
G01S 19/37
US Classification:
34235769, 34235763, 34235777
Abstract:
A satellite navigation receiver receives a combination of radio frequency signals from satellites in satellite navigation systems and process the radio frequency signals to calculate an approximate current location of the satellite navigation receiver. Satellite acquisition plays an important part in identifying the current location of the satellite navigation receiver. Acquisition involves identifying the satellites in the satellite navigation that can be used to provide navigation information. Fast Fourier transform based acquisition involves using FFT and subsequently inverse FFT (IFFT) to correlate a coarse acquisition (C/A) code transmitted by a satellite with a C/A code locally generated on the GPS receiver to identify and acquire a transmitting satellite.
System And Method For Improving Throughput Of Data Transfers Using A Shared Non-Deterministic Bus
US Patent:
8566491, Oct 22, 2013
Filed:
Jul 19, 2011
Appl. No.:
13/186416
Inventors:
Srinjoy Das - Solana Beach CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 13/18
G06F 13/364
G06F 13/16
G11C 7/10
G06F 13/364
G06F 13/16
G11C 7/10
US Classification:
710118, 710116, 710241, 710244, 711169
Abstract:
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
System And Method For Facilitating Data Transfer Using A Shared Non-Deterministic Bus
US Patent:
2012019, Aug 2, 2012
Filed:
Jul 19, 2011
Appl. No.:
13/186391
Inventors:
Srinjoy Das - Solana Beach CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
International Classification:
H04L 27/00
H04B 1/707
H04B 1/707
US Classification:
375147, 375316, 375E01002
Abstract:
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
System And Method For Managing A Memory As A Circular Buffer
US Patent:
2012019, Aug 2, 2012
Filed:
Jul 19, 2011
Appl. No.:
13/186431
Inventors:
Srinjoy Das - Solana Beach CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
International Classification:
G06F 12/00
US Classification:
711154, 711E12001
Abstract:
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
System And Method For Facilitating Data Transfer Between A First Clock Domain And A Second Clock Domain
US Patent:
2012019, Aug 2, 2012
Filed:
Jul 19, 2011
Appl. No.:
13/186441
Inventors:
Srinjoy Das - Solana Beach CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
Philip Crary - Mission Viejo CA, US
Alexander Raykhman - Irvine CA, US
International Classification:
G06F 1/04
US Classification:
713600
Abstract:
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
System And Method For Simultaneously Reading And Writing Data In A Random Access Memory
US Patent:
5802579, Sep 1, 1998
Filed:
May 16, 1996
Appl. No.:
8/648792
Inventors:
Philip D. Crary - Mission Viejo CA
Assignee:
Hughes Electronics Corporation - Los Angeles CA
International Classification:
G06F 928
G06F 938
G06F 938
US Classification:
711149
Abstract:
A system (10) and method for providing simultaneous data reading and writing for a random access memory (18) include storing new data (14) and a corresponding new data address (26), comparing the new data address to a current read address (32), and substituting (38) the new data for the data at the current read address at the output (38) while simultaneously writing the new data into the memory (18). The system and method are particularly suited for application in space-based communication satellites which utilize continuous memory read accesses since the invention provides the functionality of a dual-ported RAM while being implementable with fewer gates and less complex control circuitry to provide reduced power consumption.
Satellite Communication System Overwriting Not Validated Message Stored In Circular Buffer With New Message In Accordance With Address Stored In Last Valid Write Address Register
US Patent:
5832307, Nov 3, 1998
Filed:
Aug 19, 1996
Appl. No.:
8/697101
Inventors:
Philip D. Crary - Mission Viejo CA
Assignee:
Hughes Electronics Corporation - Los Angeles CA
International Classification:
G06F 1300
US Classification:
395872
Abstract:
A system for storing and managing messages received at a satellite communications system is disclosed. Messages are sent from a plurality of transmission sources to the system. The message data is received at a plurality of interfaces that verify the accuracy of the data sent, store it in a plurality of RAMs, and then signal a processor that a new message is available for execution. The RAMs are each part of separate message buffers that keep track of the addresses of valid, stored messages and the addresses of the last messages read from memory.
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