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Prabhjot Singh Singh, Age 4690 31St Ave, San Mateo, CA 94403

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Known as:
Prabhjot S Singh Prabhjot H Singh Prabhjot A Singh Prabhjot Singh Anand Prabhjot S Anand Prabh Jot Singh Singh Singh Prabhjot T Amand T Singh Anand Singh Prabhjot

Prabhjot Singh Phones & Addresses

90 31St Ave, San Mateo, CA 94403

Foster City, CA

Newark, NJ

Redwood City, CA

San Jose, CA

South Orange, NJ

Cambridge, MA

Berkeley, CA

Iselin, NJ

Forest Hills, NY

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Mentions for Prabhjot Singh Singh

Career records & work history

Medicine Doctors

Prabhjot Singh Photo 1

Dr. Prabhjot Singh, Avenel NJ - DDS (Doctor of Dental Surgery)

Specialties:
Oral & Maxillofacial Surgery
Address:
1030 St Georges Ave Suite B-854, Avenel, NJ 07001
(732) 750-3600 (Phone) (732) 750-3696 (Fax)
Languages:
English

Prabhjot Singh resumes & CV records

Resumes

Prabhjot Singh Photo 47

Prabhjot Singh - Fremont, CA

Work:
Carnegie Mellon University - Silicon Valley, CA Sep 2012 to Nov 2012 Tata Consultancy Services - New Delhi, Delhi 2012 to 2012
Assistant Systems Engineer NIT Jalandhar Mar 2011 to May 2011 Sensifi Inc 2010 to 2011
Software Engineer Sensifi Inc - Hyderabad, Andhra Pradesh Jun 2010 to Aug 2010
Software Engineering Intern
Education:
National Institute of Technology - Jalandhar, Punjab Jun 2011
Bachelor of Technology in Instrumentation and Control Engineering Carnegie Mellon University - Mountain View, CA
Master of Science in Software Engineering and Development Management
Prabhjot Singh Photo 48

Prabhjot Singh - Sunnyvale, CA

Work:
Little caesar - San Jose, CA Oct 2009 to Jul 2014
Manager
Education:
A.s - Punjab 2008 to 2009
High school
Prabhjot Singh Photo 49

Prabhjot Singh - Mount Holly, NC

Work:
Amcal Transportation Inc. - San Leandro, CA Oct 2011 to Dec 2011
Dispatch Biba Insurance Services, Inc. - Lathrop, CA Nov 2010 to Jan 2011
Customer Service Representative ACS - Anderson, IN Sep 2009 to Aug 2010
Theft prevention, Customer Service Allied Barton Security - Indianpolis, IN Aug 2008 to Sep 2009
Security Guard Wal Mart - Noblesville, IN Nov 2007 to Feb 2008
Grocery Stocker SGH Distributors - Corona, CA Jan 1999 to Oct 2007
Courier
Education:
La Habra High School - La Habra, CA 2004
Diploma
Skills:
Motivated, quick learner, Customer service 12 years experience

Publications & IP owners

Us Patents

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

US Patent:
7944745, May 17, 2011
Filed:
Feb 24, 2010
Appl. No.:
12/711520
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Sebastian FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 11/34
G11C 16/04
US Classification:
36518508, 36518506, 3651851, 36518517, 36518528
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

US Patent:
8345488, Jan 1, 2013
Filed:
Apr 6, 2011
Appl. No.:
13/080814
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Canyon Lake FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518529, 36518506, 36518508, 3651851
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

US Patent:
2008026, Oct 30, 2008
Filed:
Sep 25, 2007
Appl. No.:
11/861102
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Sebastian FL, US
Assignee:
INTERSIL AMERICAS INC. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518511, 36518528, 36518529
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Clock-Synced Transient Encryption

US Patent:
2022028, Sep 8, 2022
Filed:
May 26, 2022
Appl. No.:
17/804206
Inventors:
- San Francisco CA, US
Prabhjot SINGH - Union City CA, US
Assignee:
Salesforce, Inc. - San Francisco CA
International Classification:
H04L 9/32
H04L 9/40
H04L 9/08
Abstract:
A request for a transaction between a client system and a server system may be processed. The transaction may be associated with transmission of data between the client system and the server system. The data may be encrypted using a transient encryption key to form encrypted data. The transient encryption key may be a synced-clock random number configured to automatically change when a designated time interval elapses. The encrypted data may be transmitted between the client system and the server system.

Self-Healing Build Pipelines For An Application Build Process Across Distributed Computer Platforms

US Patent:
2023012, Apr 27, 2023
Filed:
Oct 21, 2021
Appl. No.:
17/507652
Inventors:
- San Francisco CA, US
Prabhjot Singh - San Francisco CA, US
Assignee:
salesforce.com, Inc. - San Francisco CA
International Classification:
G06F 8/71
G06F 9/54
Abstract:
A self-healing build pipeline architecture for a software application build job across a distributed computer platform comprises a public API that receives configuration data describing the build job, stores the configuration data in a decentralized database, serves requests to/from a pipeline tracker API, and stores states of build pipelines during the build job. The decentralized database stores the configuration data and a project identifier for the build, and metadata regarding states of the build pipelines collected across the distributed computer platform. The pipeline tracker API runs local to the build environment in the distributed computer platform and sends a build status to public API for updating the decentralized database. For any failures in any of the build pipelines, the state is retrieved from the decentralize database and a new build pipeline is triggered locally that resumes from the failed state to provide a self-healing build pipeline architecture.

Clock-Synced Transient Encryption

US Patent:
2021003, Feb 4, 2021
Filed:
Aug 2, 2019
Appl. No.:
16/530773
Inventors:
- San Francisco CA, US
Prabhjot Singh - Union City CA, US
Assignee:
Salesforce.com, Inc. - San Francisco CA
International Classification:
H04L 9/32
H04L 9/08
H04L 29/06
Abstract:
A request for a transaction between a client system and a server system may be processed. The transaction may be associated with transmission of data between the client system and the server system. The data may be encrypted using a transient encryption key to form encrypted data. The transient encryption key may be a synced-clock random number configured to automatically change when a designated time interval elapses. The encrypted data may be transmitted between the client system and the server system.

Current Sharing Scheme In Current Mode Control For Multiphase Dc-Dc Converter

US Patent:
2020038, Dec 10, 2020
Filed:
May 21, 2020
Appl. No.:
16/880814
Inventors:
- Milpitas CA, US
Prabhjot SINGH - San Jose CA, US
Long Robin YU - Zhejiang, CN
Assignee:
Renesas Electronics America Inc. - Milpitas CA
International Classification:
H02M 3/158
H02M 1/00
Abstract:
The present embodiments relate generally to DC-DC converters and more particularly to a scheme for providing current sharing between parallel converters in a multiphase configuration. In some embodiments, a cycle-by-cycle instant correction to the compensation signal offset is provided based on the current share error between the paralleled converters so as to achieve improved instant current share performance.

Cross Account Access For A Virtual Personal Assistant Via Voice Printing

US Patent:
2020026, Aug 20, 2020
Filed:
Feb 19, 2019
Appl. No.:
16/278967
Inventors:
- San Francisco CA, US
Prabhjot SINGH - Union City CA, US
International Classification:
G10L 15/32
G10L 15/22
G10L 17/00
G06F 9/451
G06F 21/32
Abstract:
A method for accessing a virtual personal assistant has been developed. First, a trust relationship is established between a primary smart speaker device that allows a user to access the virtual personal assistant with voice commands and a separate secondary smart speaker device. A trust relationship is established by generating a request at the secondary smart speaker device to allow access the virtual personal assistant with voice print authentication from the user and then validating the request at the primary smart speaker device to confirm the authenticity of the request. Next, a voice input is received from the user at the secondary smart speaker device requesting access to the virtual personal assistant. The identity of the user is verified using voice print identification with the secondary smart speaker device. Access for the user is then granted to the virtual personal assistant using the secondary smart speaker device.

Possible Relatives

D Singh  Dawinder S Singh  Dawn M Singh  Daya K Singh  Dale R Singh  Daljeet Singh  Aaron Singh  Prabhjot Sidhu  Prabhjot S Deol  Prabhjot K Kahlon 

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