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Prasad L Sastry, Age 621064 Ridgemont Dr, Milpitas, CA 95035

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Known as:
Prasad Roopa Sastry Hebbal L Sastry Sastry Prasad Lakshmana Sastry Prasad
Related to:
Roopa Cheluvaiah Sastry 57

Prasad Sastry Phones & Addresses

1064 Ridgemont Dr, Milpitas, CA 95035 (408) 942-8595

Durham, NC

Santa Clara, CA

Mentions for Prasad L Sastry

Prasad Sastry resumes & CV records

Resumes

Prasad Sastry Photo 13

Ic Design

Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Xilinx since Feb 1995
ic design
Prasad Sastry Photo 14

--Lean / Six Sigma Manufacturing Transformation Expert

Location:
United States

Publications & IP owners

Us Patents

User Configurable Memory System Having Local And Global Memory Blocks

US Patent:
6662285, Dec 9, 2003
Filed:
Jul 27, 2001
Appl. No.:
09/917304
Inventors:
Stephen M. Douglass - Saratoga CA
Prasad L. Sastry - Milpitas CA
Mehul R. Vashi - San Jose CA
Robert Yin - Castro Valley CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 1200
US Classification:
711167, 712 37, 713 1, 326 37
Abstract:
A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Programmable Logic Device With Configurable Power Supply

US Patent:
5661685, Aug 26, 1997
Filed:
Sep 25, 1995
Appl. No.:
8/533131
Inventors:
Napoleon W. Lee - Milpitas CA
Derek R. Curd - San Jose CA
Sholeh Diba - Los Gatos CA
Prasad Sastry - Milpitas CA
Mihai G. Statovici - San Jose CA
Kameswara K. Rao - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 700
US Classification:
36518522
Abstract:
An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

Possible Relatives

Rama G Sastry  Prasad R Joshi  Prasad S Kulkarni  Prasad M Varghese  Prasad V Hardas  Prasad L Manikonda  Prasad S Margasahayam 

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