Quinn Able Jacobson, Age 51598 Sunnymount Ave, Sunnyvale, CA 94087

6757807, Jun 29, 2004

Aug 18, 2000

09/642075

Quinn A. Jacobson - Sunnyvale CA
Chiao-Mei Chuang - Saratoga CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1500

712 23, 712 28, 712 34

A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different types of execution units within them. Individual Register Domains will be visible to a user.

6862664, Mar 1, 2005

May 16, 2003

10/439911

Marc Tremblay - Menlo Park CA, US
Shailender Chaudhry - San Francisco CA, US
Quinn A. Jacobson - Sunnyvale CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F012/00

711137, 711163

One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

6938130, Aug 30, 2005

Dec 15, 2003

10/737679

Quinn A. Jacobson - Sunnyvale CA, US
Marc Tremblay - Menlo Park CA, US
Shailender Chaudhry - San Francisco CA, US

Sun Microsystems Inc. - Santa Clara CA

G06F009/46
G06F009/38

711144, 711145, 711143, 711150, 711151, 711156, 711158, 711130, 710264, 710263, 710261, 710240, 710244, 718102

One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

7058877, Jun 6, 2006

May 14, 2002

10/146100

Marc Tremblay - Menlo Park CA, US
Shailender Chaudhry - San Francisco CA, US
Quinn A. Jacobson - Sunnyvale CA, US

SUN Microsystems, Inc. - Santa Clara CA

H03M 13/03

714792, 714758, 714763

A system that facilitates error correction within a register file in a central processing unit (CPU). During execution of an instruction by the CPU, the system retrieves a dataword and an associated syndrome from a source register in the register file. Next, the system uses information in the dataword and the associated syndrome to detect, and if necessary correct, an error in the dataword or associated syndrome. This error detection and correction takes place in parallel with using the dataword to perform a computational operation specified by the instruction. If an error is detected, the system prevents the instruction from performing a writeback to a destination register in the register file. The system also writes a corrected dataword to the source register in the register file. Next, the system flushes the instruction pipeline, and restarts execution of the instruction so that the corrected dataword is retrieved for the computational operation.

7089374, Aug 8, 2006

Jan 23, 2004

10/764412

Marc Tremblay - Menlo Park CA, US
Quinn A. Jacobson - Sunnyvale CA, US
Shailender Chaudhry - San Francisco CA, US
Mark S. Moir - Somerville MA, US
Maurice P. Herlihy - Brookline MA, US

SUN Microsystems, Inc. - Santa Clara CA

G06F 12/00

711145, 711130, 711143, 711144, 711150, 711151, 711156, 711158

One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.

7124331, Oct 17, 2006

May 14, 2002

10/146102

Marc Tremblay - Menlo Park CA, US
Shailender Chaudhry - San Francisco CA, US
Quinn A. Jacobson - Sunnyvale CA, US

SUN Microsystems, Inc. - Santa Clara CA

G06F 11/00

714 52

One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

7167970, Jan 23, 2007

May 23, 2005

11/135838

Quinn A. Jacobson - Sunnyvale CA, US
Shailender Chaudhry - San Francisco CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 12/08

711207

A system, which includes a processor that includes a plurality of cores, generates an address translation when there is a miss in a translation lookaside buffer (TLB). A hypervisor utilizes a translating load instruction that upon execution on the processor generates a data portion of a TLB entry. Execution of the translating load instruction utilizes information from a real-to-physical address translation table entry and information provided in the call to the translating load instruction to synthesize the data portion of a new virtual-to-physical translation table entry.

7191292, Mar 13, 2007

Jun 2, 2005

11/144097

Shailender Chaudhry - San Francisco CA, US
Quinn A. Jacobson - Sunnyvale CA, US
Ashley Saulsbury - Los Gatos CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 12/00

711133, 711 5

A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L) cache. As data is stored in a first bank of the L cache, the old data at that location is passed through the crossbar switch to a second bank of the L cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i. e. , stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.