Rafael Ignacio Aldaz, Age 484959 Blackbird Way, Pleasanton, CA 94566

Rafael Aldaz Phones & Addresses

4959 Blackbird Way, Pleasanton, CA 94566 (408) 679-0719

South Lake Tahoe, CA

Santa Clara, CA

Cupertino, CA

600 Sharon Park Dr, Menlo Park, CA 94025 (650) 561-9796

600A Sharon Park Dr, Menlo Park, CA 94025 (650) 561-9796

Mountain View, CA

Alameda, CA

Show more

Social networks

Rafael Ignacio Aldaz

Linkedin

Work

Company: Soraa Sep 1, 2010 Position: Director of advanced lightsource development

Mentions for Rafael Ignacio Aldaz

Rafael Aldaz resumes & CV records

Resumes

Rafael Aldaz Photo 13

Director Of Advanced Lightsource Development

Location:
Pleasanton, CA
Work:
Soraa
Director of Advanced Lightsource Development

Publications & IP owners

Us Patents

Method Of Forming A Dielectric Layer On A Semiconductor Light Emitting Device

US Patent:
7732231, Jun 8, 2010
Filed:
Jun 3, 2009
Appl. No.:
12/477222
Inventors:
Rafael I. Aldaz - Pleasanton CA, US
James G. Neff - Felton CA, US
Assignee:
Philips Lumileds Lighting Company, LLC - San Jose CA
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H01L 21/20
US Classification:
438 22, 438 26, 438692
Abstract:
A semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is formed. A portion of the light emitting layer and the p-type region are removed to expose a portion of the n-type region. A first metal contact is formed on an exposed portion of the n-type region and a second metal contact is formed on a remaining portion of the p-type region. The first and second metal contacts are formed on a same side of the semiconductor structure. A dielectric material is disposed between the first and second metal contacts. The dielectric material is in direct contact with a portion of the semiconductor structure, a portion of the first metal contact, and a portion of the second metal contact. A surface of the device is then planarized by removing a portion of at least one of the first metal contact, the second metal contact, and the dielectric material.

Method Of Forming A Dielectric Layer On A Semiconductor Light Emitting Device

US Patent:
7989824, Aug 2, 2011
Filed:
Apr 23, 2010
Appl. No.:
12/766221
Inventors:
Rafael I. Aldaz - Pleasanton CA, US
James G. Neff - Felton CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
Philips Lumileds Lighting Company, LLC - San Jose CA
International Classification:
H01L 33/38
US Classification:
257 91, 257E3362
Abstract:
A semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is formed. A first metal contact is formed on a portion of the n-type region and a second metal contact is formed on a portion of the p-type region. The first and second metal contacts are formed on a same side of the semiconductor structure. A dielectric material is disposed between the first and second metal contacts. The dielectric material is in direct contact with a portion of the semiconductor structure, a portion of the first metal contact, and a portion of the second metal contact. A planar surface is formed including a surface of the first metal contact, a surface of the second metal contact, and a surface of the dielectric material.

Light Emitting Device With Trenches And A Top Contact

US Patent:
8154042, Apr 10, 2012
Filed:
Apr 29, 2010
Appl. No.:
12/770550
Inventors:
Rafael I. Aldaz - Pleasanton CA, US
Aurelien J. F. David - San Francisco CA, US
Assignee:
Koninklijke Philips Electronics N V - Eindhoven
Philips Lumileds Lighting Company, LLC - San Jose CA
International Classification:
H01L 33/60
US Classification:
257 98, 257 99, 257E33068
Abstract:
A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A bottom contact disposed on a bottom surface of the semiconductor structure is electrically connected to one of the n-type region and the p-type region. A top contact disposed on a top surface of the semiconductor structure is electrically connected to the other of the n-type region and the p-type region. A mirror is aligned with the top contact. The mirror includes a trench formed in the semiconductor structure and a reflective material disposed in the trench, wherein the trench extends through the light emitting layer.

Led With Remote Phosphor Layer And Reflective Submount

US Patent:
8168998, May 1, 2012
Filed:
Jun 9, 2009
Appl. No.:
12/481021
Inventors:
Aurelien J. David - Palo Alto CA, US
Rafael I. Aldaz - Pleasanton CA, US
Mark Butterworth - Santa Clara CA, US
Serge J. Bierhuizen - Santa Rosa CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
Philips Lumileds Lighting Company, LLC - San Jose CA
International Classification:
H01L 27/15
US Classification:
257100, 257 95, 257 98, 257 99, 257E33001, 438 26, 438 27, 313502, 313512
Abstract:
A light emitting device comprises a flip-chip light emitting diode (LED) die mounted on a submount. The top surface of the submount has a reflective layer. Over the LED die is molded a hemispherical first transparent layer. A low index of refraction layer is then provided over the first transparent layer to provide TIR of phosphor light. A hemispherical phosphor layer is then provided over the low index layer. A lens is then molded over the phosphor layer. The reflection achieved by the reflective submount layer, combined with the TIR at the interface of the high index phosphor layer and the underlying low index layer, greatly improves the efficiency of the lamp. Other material may be used. The low index layer may be an air gap or a molded layer. Instead of a low index layer, a distributed Bragg reflector may be sputtered over the first transparent layer.

Light Emitting Device With Trenches And A Top Contact

US Patent:
8415656, Apr 9, 2013
Filed:
Jan 12, 2012
Appl. No.:
13/348736
Inventors:
Rafael I. Aldaz - Pleasanton CA, US
Aurelien J. F. David - San Francisco CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
Philips Limileds Lighting Company, LLC - San Jose CA
International Classification:
H01L /06
US Classification:
257 13, 257 99, 257 79, 257E33008
Abstract:
A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. A bottom contact disposed on a bottom surface of the semiconductor structure is electrically connected to one of the n-type region and the p-type region. A top contact disposed on a top surface of the semiconductor structure is electrically connected to the other of the n-type region and the p-type region. A mirror is aligned with the top contact. The mirror includes a trench formed in the semiconductor structure and a reflective material disposed in the trench, wherein the trench extends through the light emitting layer.

Silicone Based Reflective Underfill And Thermal Coupler

US Patent:
8471280, Jun 25, 2013
Filed:
Nov 6, 2009
Appl. No.:
12/613924
Inventors:
Rafael I. Aldaz - Pleasanton CA, US
Grigoriy Basin - San Francisco CA, US
Paul S. Martin - Singapore, SG
Michael Krames - Los Altos CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H01L 23/29
US Classification:
257 98, 257788, 257789, 257791, 257795, 257E23023
Abstract:
In one embodiment, a flip chip LED is formed with a high density of gold posts extending from a bottom surface of its n-layer and p-layer. The gold posts are bonded to submount electrodes. An underfill material is then molded to fill the voids between the bottom of the LED and the submount. The underfill comprises a silicone molding compound base and about 70-80%, by weight, alumina (or other suitable material). Alumina has a thermal conductance that is about 25 times better than that of the typical silicone underfill, which is mostly silica. The alumina is a white powder. The underfill may also contain about 5-10%, by weight, TiOto increase the reflectivity. LED light is reflected upward by the reflective underfill, and the underfill efficiently conducts heat to the submount. The underfill also randomizes the light scattering, improving light extraction. The distributed gold posts and underfill support the LED layers during a growth substrate lift-off process.

Semiconductor Light Emitting Device Including Graded Region

US Patent:
8507929, Aug 13, 2013
Filed:
Jun 16, 2008
Appl. No.:
12/139999
Inventors:
Patrick N. Grillot - San Jose CA, US
Rafael I. Aldaz - Santa Clara CA, US
Eugene I. Chen - Palo Alto CA, US
Sateria Salim - San Jose CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H01L 33/00
H01L 33/12
H01L 21/00
US Classification:
257 97, 257 94, 257 95, 257 96, 257E33023, 257E33032, 438 46, 438 47
Abstract:
One or more regions of graded composition are included in a III-P light emitting device, to reduce the Vassociated with interfaces in the device. In accordance with embodiments of the invention, a semiconductor structure comprises a III-P light emitting layer disposed between an n-type region and a p-type region. A graded region is disposed between the p-type region and a GaP window layer. The aluminum composition is graded in the graded region. The graded region may have a thickness of at least 150 nm. In some embodiments, in addition to or instead of a graded region between the p-type region and the GaP window layer, the aluminum composition is graded in a graded region disposed between an etch stop layer and the n-type region.

Led With Remote Phosphor Layer And Reflective Submount

US Patent:
8536608, Sep 17, 2013
Filed:
Mar 29, 2012
Appl. No.:
13/433424
Inventors:
Aurelien Jean Francois David - San Francisco CA, US
Rafael I. Aldaz - Pleasanton CA, US
Mark Melvin Butterworth - Santa Clara CA, US
Serge J. A. Bierhuizen - San Jose CA, US
Assignee:
Koninklijke Philips N.V. - Eindhoven
International Classification:
H01L 33/00
H01L 21/00
US Classification:
257 98, 257 95, 257 99, 257100, 257E33001, 438 26, 438 27, 313502, 313512
Abstract:
A light emitting device comprises a flip-chip light emitting diode (LED) die mounted on a submount. The top surface of the submount has a reflective layer. Over the LED die is molded a hemispherical first transparent layer. A low index of refraction layer is then provided over the first transparent layer to provide TIR of phosphor light. A hemispherical phosphor layer is then provided over the low index layer. A lens is then molded over the phosphor layer. The reflection achieved by the reflective submount layer, combined with the TIR at the interface of the high index phosphor layer and the underlying low index layer, greatly improves the efficiency of the lamp. Other material may be used. The low index layer may be an air gap or a molded layer. Instead of a low index layer, a distributed Bragg reflector may be sputtered over the first transparent layer.

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.