Rainer Cornelia G Thoma, Age 63Madonna, VT

6373100, Apr 16, 2002

Mar 4, 1998

09/033628

Irenee M. Pages - Villeneuve Tolosane, FR
Quang X. Nguyen - Castanet-Tolosan, FR
Cynthia Trigas - Munich, DE
Rainer Thoma - Gilbert AZ
Jeffrey Pearse - Chandler AZ

Semiconductor Components Industries LLC - Phoenix AZ

H01L 2976

257343, 257329, 257341

A vertically diffused FET ( ) is fabricated on a semiconductor die ( ) that includes an N substrate ( ) and an N epitaxial layer ( ). The FET ( ) has a source region ( ) and a channel region ( ) near a front surface ( ) of the epitaxial layer ( ), and a drain region in the substrate ( ). A trench ( ) extends through the epitaxial layer ( ) to the substrate ( ). A conductive layer ( ) fills the trench ( ), thereby forming a conductive plug ( ) electrically coupled to the substrate ( ). The conductive plug ( ) forms a top side drain electrode of the FET ( ).

6551869, Apr 22, 2003

Jun 9, 2000

09/590461

Francis K. Chai - Gilbert AZ
Vida Ilderem Burger - Phoenix AZ
Carl S. Kyono - Tempe AZ
Sharanda L. Bigelow - Chandler AZ
Rainer Thoma - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H01L 218238

438204, 438236, 438316, 438325, 438335, 257557, 257575

A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

6563181, May 13, 2003

Nov 2, 2001

10/003535

Yang Du - Austin TX
Suman Kumar Banerjee - Mesa AZ
Rainer Thoma - Gilbert AZ
Alain Duvallet - Austin TX

Motorola, Inc. - Schaumburg IL

H01L 2996

257394, 257127, 257544, 257549, 257546, 257550, 257509, 257547, 257275

A semiconductor device ( ) includes an isolated p-well ( ) formed in a substrate ( ) by a buried n-well ( ) and an n-well ring ( ). The n-well ring ( ) extends from a surface of the semiconductor device ( ) to the buried n-well ( ). The isolated p-well ( ) includes a plurality of n-well plugs ( ) extending from the surface of the semiconductor device ( ) into the isolated p-well ( ) and contacting the buried n-well ( ). The plurality of n-well plugs ( ) reduces an n-well resistance to provide better noise isolation for high frequency signals.

8453101, May 28, 2013

Nov 22, 2011

13/302350

James M. Johnson - Milton VT, US
Scott K. Springer - Burlington VT, US
Rainer Thoma - Essex Junction VT, US
Josef S. Watts - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 11/22
G06F 17/50

716136, 716134, 716133, 716112, 716111

Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e. g. , by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

8539426, Sep 17, 2013

Feb 22, 2011

13/031693

Paul A. Hyde - Essex Junction VT, US
Rainer Thoma - Essex Junction VT, US
Josef S. Watts - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G01R 25/00
G01R 27/00
G06F 17/10
G06F 17/15

716136, 716 54, 716107, 716111, 716132, 716 52, 703 2, 703 16, 702 65, 702 66, 702117, 702124, 702190

A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

2021013, May 6, 2021

Nov 1, 2019

16/671414

- Santa Clara CA, US
Rainer Thoma - Essex Junction VT, US
Harsh Shah - South Burlington VT, US
Anindya Nath - Essex Junction VT, US

H01L 23/528
H01L 23/522
H01L 29/417
H01L 21/74

Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.