Rajeev Dinkar Joshi, Age 65Cupertino, CA

6469384, Oct 22, 2002

Feb 1, 2001

09/776341

Rajeev Joshi - Cupertino CA

Fairchild Semiconductor Corporation - DE

H01L 2348

257738, 257723

A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

6489678, Dec 3, 2002

Mar 15, 1999

09/285191

Rajeev Joshi - Cupertino CA

Fairchild Semiconductor Corporation

H01L 2334

257723, 257737, 257666, 257693

A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

6566749, May 20, 2003

Jan 15, 2002

10/050428

Rajeev Joshi - Cupertino CA
Steven Sapp - Felton CA

Fairchild Semiconductor Corporation - South Portland ME

H01L 2310

257706, 257712, 257678, 257784, 257589

A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.

6627991, Sep 30, 2003

Apr 10, 2000

09/546053

Rajeev Joshi - Cupertino CA

Fairchild Semiconductor Corporation - South Portland ME

H01L 2334

257723, 257666, 257778, 257693, 257738

A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

6633030, Oct 14, 2003

Aug 31, 2001

09/944717

Rajeev Joshi - Cupertino CA

Fiarchild Semiconductor - South Protland ME

H01L 3100

2502141, 250239

An optocoupler package is disclosed. The optocoupler package comprises a carrier substrate and a plurality of conductive regions on the carrier substrate. An optoelectronic device, an optically transmissive medium, and a plurality of conductive structures can be on the carrier substrate.

6661082, Dec 9, 2003

Jul 19, 2000

09/619115

Honorio T. Granada - Cebu, PH
Rajeev Joshi - Cupertino CA
Connie Tangpuz - Lapulapu, PH

Fairchild Semiconductor Corporation - South Portland ME

H01L 23495

257676, 257738, 257778, 257713, 22818022

A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

6683375, Jan 27, 2004

Jun 15, 2001

09/881787

Rajeev Joshi - Cupertino CA
Chung-Lin Wu - San Jose CA

Fairchild Semiconductor Corporation - South Portland ME

H01L 2348

257690, 257691, 257692, 257693, 257698, 257730

A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

6696321, Feb 24, 2004

Dec 3, 2002

10/309661

Rajeev Joshi - Cupertino CA

Fairchild Semiconductor, Corporation - South Portland ME

H01L 2144

438111, 438108, 438123

A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.