Reginald Wilcox1011 Cady Hill Rd, Binghamville, VT 05444

2003020, Oct 23, 2003

Apr 23, 2002

10/063427

Bette Bergman Reuter - Essex Junction VT, US
Mitchell DeHond - Essex Junction VT, US
William Leipold - Enosburg Falls VT, US
Daniel Maynard - Craftsbury Common VT, US
Brian Pfeifer - Red Hook NY, US
David Reynolds - Essex Junction VT, US
Reginald Wilcox - Cambridge VT, US

International Business Machines Corporation - Armonk NY

G06F017/50

716/004000

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

6305004, Oct 16, 2001

Aug 31, 1999

9/387062

Gustavo Tellez - Cornwall on Hudson NY
Gary Doyle - Jonesville VT
Philip Honsinger - Poughkeepsie NY
Steven Lovejoy - South Burlington VT
Charles Meiley - San Jose CA
Gorden Starkey - Essex Junction VT
Reginald Wilcox - Cambridge VT

International Business Machines Corporation - Armonk NY

G06F 1750

716 12

A method for automatically wiring (i. e. , routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.

5587857, Dec 24, 1996

Oct 18, 1994

8/324841

Steven H. Voldman - Burlington VT
Albert J. Wallash - Morgan Hill CA
Reginald B. Wilcox - Cambridge VT

International Business Machines Corporation - Armonk NY

G11B 2121

360103

An MR head has its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to a silicon chip substrate ground potential or to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the wafer level to ultimate completion of individual sliders.

5559051, Sep 24, 1996

Dec 23, 1994

8/363465

Steven H. Voldman - Burlington VT
Albert J. Wallash - Morgan Hill CA
Reginald B. Wilcox - Cambridge VT

International Business Machines Corporation - Armonk NY

H01L 2128
H01L 21301
H01L 21304
H01L 2148

437 51

A process of making an MR head having its MR stripe protected from electro-static discharge (ESD) on a slider, such as titanium carbide. The MR stripe is protected by a plurality of silicon integrated circuit devices which conduct ESD-induced current from the MR stripe to larger components in the MR head such as the first and second shield layers and the coil layer. In a preferred embodiment the integrated circuit devices and interconnects are constructed in a single crystal silicon chip. The silicon chip is fixedly mounted to a trailing edge of the slider and the MR head is mounted on a trailing edge of the silicon chip adjacent the integrated circuit devices. The invention includes a method of mass producing sliders by combining thin film technology for making MR heads with integrated circuit technology for making integrated circuit devices. These technologies are combined at the row level to ultimate completion of individual sliders. A silicon wafer, including the integrated circuit devices, is sliced into a plurality of silicon bars, each bar including a row of circuit devices.