Richard Earl Warmke, Age 56Reno, NV

Richard Warmke Phones & Addresses

Reno, NV

11979 Stoney Creek Rd, Truckee, CA 96161 (530) 214-8153

26815 Ortega Dr, Los Altos Hills, CA 94022 (650) 941-9001 (650) 941-9007 (650) 559-9070

1245 Magnolia Ave, San Jose, CA 95126 (408) 286-9870 (408) 971-7765

1220 Magnolia Ave, San Jose, CA 95126

Washoe, NV

1245 Magnolia Ave, San Jose, CA 95126 (408) 307-3477

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Work

Position: Sales Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Richard Earl Warmke

Publications & IP owners

Us Patents

Apparatus For Data Recovery In A Synchronous Chip-To-Chip System

US Patent:
6570944, May 27, 2003
Filed:
Jun 25, 2001
Appl. No.:
09/891184
Inventors:
Scott C. Best - Palo Alto CA
Richard E. Warmke - San Jose CA
David B. Roberts - San Jose CA
Frank Lambrecht - Mountain View CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 700
US Classification:
375355, 375360, 375362, 375375, 370517, 327161, 327162, 714731, 714744
Abstract:
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Stacked Semiconductor Module

US Patent:
6720643, Apr 13, 2004
Filed:
Feb 22, 2001
Appl. No.:
09/792788
Inventors:
Thomas F. Fox - Palo Alto CA
Sayeh Khalili - San Jose CA
Belgacem Haba - Cupertino CA
David Nguyen - San Jose CA
Richard Warmke - San Jose CA
Xingchao Yuan - Palo Alto CA
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
H01L 2302
US Classification:
257686, 257777, 257723
Abstract:
The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.

Granularity Memory Column Access

US Patent:
6825841, Nov 30, 2004
Filed:
Sep 7, 2001
Appl. No.:
09/949464
Inventors:
Craig E. Hampel - San Jose CA
Richard E. Warmke - San Jose CA
Frederick A. Ware - Los Altos CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
G06F 1576
US Classification:
345519, 345545, 345567
Abstract:
A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Apparatus For Data Recovery In A Synchronous Chip-To-Chip System

US Patent:
6836503, Dec 28, 2004
Filed:
Jan 28, 2003
Appl. No.:
10/353608
Inventors:
Scott C. Best - Palo Alto CA
Richard E. Warmke - San Jose CA
David B. Roberts - San Jose CA
Frank Lambrecht - Mountain View CA
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 700
US Classification:
375 35, 375360, 375362, 375375, 370517, 714731, 714744
Abstract:
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Stacked Semiconductor Module

US Patent:
7037757, May 2, 2006
Filed:
Feb 20, 2004
Appl. No.:
10/783822
Inventors:
Thomas F. Fox - Palo Alto CA, US
Sayeh Khalili - San Jose CA, US
Belgacem Haba - Cupertino CA, US
David Nguyen - San Jose CA, US
Richard Warmke - San Jose CA, US
Xingchao Yuan - Palo Alto CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H01L 21/44
H01L 21/48
H01L 21/50
US Classification:
438109, 438108
Abstract:
The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Stacked Semiconductor Module

US Patent:
7285443, Oct 23, 2007
Filed:
Mar 16, 2006
Appl. No.:
11/378008
Inventors:
Thomas F. Fox - Palo Alto CA, US
Sayeh Khalili - San Jose CA, US
Belgacem Haba - Cupertino CA, US
David Nguyen - San Jose CA, US
Richard Warmke - San Jose CA, US
Xingchao Yuan - Palo Alto CA, US
Assignee:
Rambus, Inc. - Los Altos CA
International Classification:
H01L 21/44
H01L 21/48
H01L 21/50
US Classification:
438108, 438109, 438124, 257E21503
Abstract:
The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Apparatus For Data Recovery In A Synchronous Chip-To-Chip System

US Patent:
7349510, Mar 25, 2008
Filed:
May 24, 2004
Appl. No.:
10/852864
Inventors:
Scott C. Best - Palo Alto CA, US
Richard E. Warmke - San Jose CA, US
David B. Roberts - San Jose CA, US
Frank Lambrecht - Mountain View CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 7/00
US Classification:
375355, 375360, 375362, 375375, 370517, 327161, 327162, 714731, 714744
Abstract:
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Apparatus For Data Recovery In A Synchronous Chip-To-Chip System

US Patent:
7627066, Dec 1, 2009
Filed:
Mar 25, 2008
Appl. No.:
12/079388
Inventors:
Scott C. Best - Palo Alto CA, US
Richard E. Warmke - San Jose CA, US
David B. Roberts - San Jose CA, US
Frank Lambrecht - Mountain View CA, US
Assignee:
Rambus Inc. - Los Altos CA
International Classification:
H04L 7/00
US Classification:
375355, 375360, 375362, 375375, 370517, 327161, 327162, 714731, 714744
Abstract:
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

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