Robert L Chatham, Age 555460 Wallingford Arch, Virginia Beach, VA 23464

Robert Chatham Phones & Addresses

5460 Wallingford Arch, Virginia Bch, VA 23464 (757) 233-9498

3868 Border Way, Virginia Bch, VA 23456

Virginia Beach, VA

Seaside, CA

2371 Peacock Valley Rd, Chula Vista, CA 91915 (619) 216-6960

San Diego, CA

Newport, RI

Ewa Beach, HI

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Mentions for Robert L Chatham

Career records & work history

Lawyers & Attorneys

Robert Chatham Photo 1

Robert Chatham - Lawyer

ISLN:
1000833110
Admitted:
2018
Robert Chatham Photo 2

Robert Chatham - Lawyer

Office:
Chatham & Hogan, LLP
Specialties:
Business Law, Litigation
ISLN:
918883894
Admitted:
2005
University:
University of Virginia, B.A., 2000
Law School:
Southwestern University School of Law, J.D., 2005
Robert Chatham Photo 3

Robert Paul Chatham, La Mesa CA - Lawyer

Office:
4840 Cypress St., La Mesa, CA
Specialties:
Government, Military Law, Criminal Law, Civil Litigation, Tort Litigation, Medical Law
ISLN:
916380968
Admitted:
1999
University:
California Lutheran University, B.A.
Law School:
Boston University, J.D.

Robert Chatham resumes & CV records

Resumes

Robert Chatham Photo 46

Robert Bonneau Chatham

Robert Chatham Photo 47

Robert Chatham

Skills:
Planning
Robert Chatham Photo 48

Robert Chatham

Robert Chatham Photo 49

Engineering Test And Certification At Urs Corporation

Position:
Engineering Test and Certification at URS Corporation
Location:
Norfolk, Virginia Area
Industry:
Military
Work:
URS Corporation - Norfolk, Virginia Area since Aug 2011
Engineering Test and Certification
Commander Second Fleet Nov 2010 - Aug 2011
Training Monitor
ACU2 May 2009 - Nov 2010
Commanding Officer
ACU 2 Jan 2008 - Jan 2009
Executive Officer
Surface Forces Atlantic Nov 2005 - Oct 2007
Flag Secretary
USS McCampbell (DDG85) Apr 2004 - Oct 2005
Executive Officer
Commander Naval Forces Pacific Nov 2002 - Jan 2004
Staff Action Officer
Afloat Training Group Pacific Feb 2001 - Nov 2001
Engineering Gas Turbine Readiness Trainer and Assessor
USS Decatur (DDG73) Jun 1999 - Feb 2001
Chief Engineer
USS Cushing (DD985) Jun 1995 - Dec 1996
Main Propulsion Assistant
USS Nimitz (CVN68) Apr 1992 - May 1995
Division Officer
Education:
Naval Postgraduate School 1997 - 1998
MA, National Security Affairs
University of South Carolina-Columbia 1987 - 1991
BA, History
Honor & Awards:
Meritorious Service Medal (3) Navy Commendation Medal (3) Navy Achievement Medal (1) Navy Meritorious Unit Commendation Medal (1) Battle Efficiency Award (3) National Defense Service Medal Armed Forces Expeditionary Medal South West Asia Service Medal Global War on Terrorism Expeditionary Medal Global War on Terrorism Service Medal
Robert Chatham Photo 50

Environmental, Health And Safety At Pseg

Location:
United States
Industry:
Utilities

Publications & IP owners

Us Patents

Uniform Batch Film Deposition Process And Films So Produced

US Patent:
2007001, Jan 11, 2007
Filed:
Jul 7, 2006
Appl. No.:
11/482887
Inventors:
Robert Bailey - Santa Cruz CA, US
Taiqing Qiu - Los Gatos CA, US
Cole Porter - San Jose CA, US
Olivier Laparra - San Jose CA, US
Robert Chatham - Scotts Valley CA, US
Martin Mogaard - Scotts Valley CA, US
Helmuth Treichel - Milpitas CA, US
Assignee:
Aviza Technology, Inc. - Scotts Valley CA
International Classification:
H01L 21/20
US Classification:
438478000
Abstract:
A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant. A process for forming such a batch of wafer substrates involves feeding the precursor into a reactor containing a batch of wafer substrates and reacting the precursor at a wafer substrate temperature, total pressure, and precursor flow rate sufficient to create such a layer of material. The delivery of a precursor and co-reactant as needed through vertical tube injectors having multiple orifices with at least one orifice in registry with each of the batch of wafer substrates and exit slits within the reactor to create flow across the surface of each of the wafer substrates in the batch provides the within-wafer and wafer-to-wafer uniformity.

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