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Robert J Volentine, Age 66728 Veridian Cir NW, Palm Bay, FL 32907

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Known as:
Robert James Volentine Robert Jordan Volentine Robert M Volentine Robert J Valentine Robt J Volentine

Robert Volentine Phones & Addresses

18711 Hardy Trace Dr, Tomball, TX 77377

4539 Wandering Vine Trl, Round Rock, TX 78665 (512) 388-5350

4000 Lindo Loop, Round Rock, TX 78681

8718 Candleshine Cir, Houston, TX 77095

17102 Sandestine Dr, Houston, TX 77095

San Antonio, TX

Plymouth, MN

Cedar Park, TX

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Mentions for Robert J Volentine

Robert Volentine resumes & CV records

Resumes

Robert Volentine Photo 8

Sr. S/W Engineer At Dell, Inc

Position:
Senior Software Engineer Consultant at Dell, inc
Location:
Austin, Texas Area
Industry:
Computer Hardware
Work:
Dell, inc since Mar 2005
Senior Software Engineer Consultant Hewlett Packard May 2002 - Mar 2005
Senior Software Engineer Compaq Nov 1994 - May 2002
Senior Member Technical Staff
Education:
Trinity University 1978 - 1982
BS, Engineering Science, Electical Engineering
Honor & Awards:
PAT. NO. 7,130,950 Providing Access to Memory Configuration Information in a Commputer PAT. NO. 6,363,473 Simulated Memory Stack in a Stackless Environment PAT. NO. 7,480,790 Sleep State Resume PUB. APP. NO. 20050246517 (Pat Pending) Method for Ensuring Optimal Memory Configuration in a Computer
Robert Volentine Photo 9

Medical Lab Technology Student

Position:
Student at Austin Community College
Location:
United States
Industry:
Medical Practice
Work:
Austin Community College since Jan 2013
Student Austin Community College Jan 2012 - Dec 2012
Student University of Texas String Project 2008 - 2011
Faculty MuMu English May 2009 - Aug 2009
Teacher
Education:
Austin Community College 2013 - 2015
medical lab, science/medicine The University of Texas at Austin 2008 - 2012
Sogang University 2009 - 2009
Interests:
Computer Programming: C++, Java, Python, Assembly, others Languages: Chinese, Japanese, Korean Music: Cello, Piano, Music Composition Art: 3D modeling, Chinese Calligraphy Business: general business practices Productivity Methods: mission statements, scheduling, goal-setting
Languages:
English
Korean
Japanese
Chinese

Publications & IP owners

Us Patents

Providing Access To Memory Configuration Information In A Computer

US Patent:
7130950, Oct 31, 2006
Filed:
Apr 30, 2004
Appl. No.:
10/837335
Inventors:
Robert J. Volentine - Houston TX, US
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
G06F 13/24
G06F 12/00
US Classification:
710260, 710261, 711200
Abstract:
Client software stores an identifier corresponding to memory configuration data of interest and causes a software interrupt that requests a memory configuration read function. An interrupt read function handler then reads the data of interest responsive to the identifier and returns the data of interest. The client software may include, for example, BIOS firmware or application software executing in real or protected mode. The memory configuration information may be stored in a hidden I/O or MMIO register device. In such an embodiment, the interrupt handler may enable access to the hidden I/O or MMIO register device prior to reading the data of interest and disable access to the hidden I/O or MMIO register device afterwards.

Sleep State Resume

US Patent:
7480790, Jan 20, 2009
Filed:
Jul 29, 2005
Appl. No.:
11/192805
Inventors:
Louis B. Hobson - Tomball TX, US
Robert Volentine - Round Rock TX, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/00
G06F 15/177
US Classification:
713 1, 713 2, 713100
Abstract:
In one embodiment a method comprises collecting device configuration information during an initialization process in a computing device, storing the device configuration in a memory buffer, and using the device configuration information to restore the computing device from a low-power mode to an operational mode.

Method For Ensuring Optimal Memory Configuration In A Computer

US Patent:
7681023, Mar 16, 2010
Filed:
Apr 30, 2004
Appl. No.:
10/836574
Inventors:
Robert J. Volentine - Houston TX, US
Mark A. Piwonka - Tomball TX, US
Patrick L. Gibbons - Magnolia TX, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/00
G06F 15/177
G06F 12/06
G06F 13/00
G06F 13/28
US Classification:
713 1, 713 2, 713100, 711 5, 711115, 711157
Abstract:
A method according to the invention ensures optimal memory configuration in a computer: A determination is made whether performance can be improved by rearranging the DIMMs that are installed in the computer. If so, then a user of the computer is notified that the DIMMs can be rearranged to improve performance.

System And Method Of Managing Bios Test Routnes

US Patent:
7895472, Feb 22, 2011
Filed:
May 21, 2008
Appl. No.:
12/124331
Inventors:
Natalie N. Quach - Austin TX, US
Mark W. Shutt - Austin TX, US
Peter Cloney - Round Rock TX, US
Robert J. Volentine - Round Rock TX, US
Assignee:
Dell Products, LP - Round Rock TX
International Classification:
G06F 11/00
US Classification:
714 27, 714 36
Abstract:
A system and method of a basic input output system (BIOS) test system are disclosed. According to an aspect, a basic input output system (BIOS) test system can include a BIOS test manager configured to enable BIOS testing of multiple information handling systems within a test environment. The BIOS test system can also include a local test harness driver operable to be coupled to the remote BIOS test manager to receive test routines, and a test buffer configured to receive a test routine from the BIOS test manager. The test routine can further be executed using a test engine integrated as a part of a BIOS of a particular information handling system.

Synchronizing Processors When Entering System Management Mode

US Patent:
7991933, Aug 2, 2011
Filed:
Jun 25, 2008
Appl. No.:
12/145570
Inventors:
Juan Francisco Diaz - Round Rock TX, US
Dirie N. Herzi - Round Rock TX, US
Robert Volentine - Round Rock TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 13/24
G06F 1/12
US Classification:
710261, 710267, 713375
Abstract:
A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

Self Test Initialization

US Patent:
8103862, Jan 24, 2012
Filed:
Jun 25, 2008
Appl. No.:
12/145691
Inventors:
Madhusudhan Rangarajan - Round Rock TX, US
Robert Volentine - Round Rock TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 15/177
US Classification:
713 1, 713 2, 713100
Abstract:
A system to perform an information handling system (IHS) initialization includes one or more subsystems to receive a command to power on the IHS, initialize a processor cache memory to emulate a random access memory (RAM), determine whether a manufacturing self test is being performed on the IHS, and in response to the manufacturing self test being performed, complete the initialization without a complete memory initialization.

System And Method For Memory Architecture Configuration

US Patent:
8122208, Feb 21, 2012
Filed:
Mar 25, 2009
Appl. No.:
12/411105
Inventors:
Vijay Nijhawan - Austin TX, US
Robert Volentine - Round Rock TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 12/00
US Classification:
711157, 711170, 711E12079
Abstract:
Systems and methods for reducing problems and disadvantages associated with physically asymmetrical memory structures are disclosed. A method for configuring memories in an information handling system having a plurality of memories, each memory local to one of a plurality of nodes, and wherein at least one memory of the plurality of memories has a different memory capacity than at least one other memory of the plurality of memories is provided. The method may include determining a smallest memory capacity of the plurality of memories. The method may also include allocating a node-interleaved memory using a portion of each memory equal to the smallest memory capacity. For each particular memory not fully allocated to the node-interleaved memory, each portion of each particular memory not allocated to the node-interleaved memory may be associated with a node local to the particular memory.

Processor Interrupt Command Response System

US Patent:
8260995, Sep 4, 2012
Filed:
Jul 7, 2011
Appl. No.:
13/178050
Inventors:
Juan Francisco Diaz - Round Rock TX, US
Dirie N. Herzi - Round Rock TX, US
Robert Volentine - Round Rock TX, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 13/24
G06F 1/12
US Classification:
710261, 710267, 713375
Abstract:
A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Possible Relatives

Linda J Volentine  Susan Z Volentine  Beverly Volentine  Robert R Last  Robert C Stanbery  Robert C Standard  Robert E Standefer  Robert R Standfield  Robert J Stangel  Robert P Stanhope 

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