Russell L Nicol, Age 642109 N Gooder St, Eau Claire, WI 54703

8498315, Jul 30, 2013

Oct 10, 2011

13/270002

Paul R. Frank - Eau Claire WI, US
Gregory M. Thorson - Altoona WI, US
Russell L. Nicol - Eau Claire WI, US
Donglai Dai - Pleasanton CA, US
Joseph M. Placek - Chippewa Falls WI, US

Silicon Graphics International Corp. - Fremont CA

H04J 3/06

370503

A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.

2008016, Jul 10, 2008

Jan 5, 2007

11/620215

Paul R. Frank - Eau Claire WI, US
Gregory M. Thorson - Altoona WI, US
Russell L. Nicol - Eau Claire WI, US
Donglai Dai - Eau Claire WI, US
Joseph M. Placek - Chippewa Falls WI, US

SILICON GRAPHICS, INC. - Sunnyvale CA

G06F 15/16
H04L 12/28

709248, 370254

A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.

2018015, Jun 7, 2018

Dec 6, 2016

15/370529

- Milpitas CA, US
Russell L. Nicol - Eau Claire WI, US

H04L 12/873
H04L 12/931
H04L 12/801

This patent application relates generally to a shared-credit arbitration circuit for use in arbitrating access by a number of virtual channels to a shared resource managed by a destination (arbiter) based on credits allotted to each virtual channel, in which only the destination is aware of the availability of a shared pool of resources, and the destination selectively provides access to the shared pool by the virtual channels and returns credits to the source(s) associated with the virtual channels when shared resources are used so that the source(s) are unaware of the destination's use of the shared resources and are unhindered by the destination's use of shared resources. Among other things, this can significantly reduce the complexity of the source(s) and the required handshaking between the source(s) and the destination.

2016037, Dec 22, 2016

Jun 17, 2015

14/742007

- Milpitas CA, US
Randal Steven Passint - Chippewa Falls WI, US
Joseph Martin Placek - Chippewa Falls WI, US
Russell Leonard Nicol - Eau Claire WI, US

H04L 29/06
H04L 1/00
H04L 29/08

Various embodiments improve the operation of computers by providing methods of transmitting data with low latency and high bandwidth. Data may be transmitted in a packet composed of data flits, the data flits having at least two different formats configured to implement different communication protocols. In some embodiments, a given flit may be transmitted using two different modulation methods, with a first part of the flit transmitted using a first modulation method, such as a binary method, and a second part of the flit using a higher-order modulation method.