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Russell D Nielsen, Age 5530450 N Gunsight Rd, Athol, ID 83801

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Known as:
Russell Dean Nielsen Rusty Dean Nielsen Rusty D Nielsen Russ D Nielsen Russd Nielsen Dean Nielsen Russ Dean Nielsen Russell
Related to:
Christina M Slaughter 55

Russell Nielsen Phones & Addresses

Athol, ID

1906 Lemhi St, Boise, ID 83705

Nampa, ID

Kuna, ID

11932 W Cedarstone St, Boise, ID 83709

Work

Company: Debt reduction services Nov 2009 Position: It specialist

Education

School / High School: ITT Tech- Boise, ID 2012 Specialities: Associates in Network Systems Administration

Skills

Active Directory • Exchange • Windows Server 2008 • Windows Server 2012 • Microsoft Office 2010 • DNS Server

Mentions for Russell D Nielsen

Russell Nielsen resumes & CV records

Resumes

Russell Nielsen Photo 31

Book Author

Location:
Salt Lake City, UT
Industry:
Security And Investigations
Work:
Security Industry Specialists, Inc. - South Jordan, Utah Mar 2011 - Apr 2013
Safety and Security Officer Centurion Security - Provo, Utah Area Aug 2009 - Jun 2010
Security Officer/Mobile Patrol Provo City 2008 - 2010
Transport Officer
Education:
Utah Valley University 2008 - 2009
Police Academy, Law Enforcement Utah Valley University 2008 - 2009
S.F.O. CertifiedL.E.O, Certifiable Weber State University 2006 - 2007
Mountain View High School 2002 - 2005
High School Diploma, Applied Technology, Health Occupations
Skills:
Security, Security Operations, Enforcement, Physical Security, Tactics, Corporate Security, Microsoft Office, Patrol, Cctv, Security Management, Leadership, Self Defense, Defence Sector, Executive Protection, Personal Security, Surveillance, Risk Assessment, Access Control, Arrest Control, Defensive Tactics, Drug Testing, Dispatching, Typing, Utah Laws, Asp/Baton Tactics, Oc/Pepper Spray Trained, Hard Worker, Motivated, Team Player, Personal Protection, Teamwork, Private Investigations, Security Training, Supervisory Skills, Weapons, Workplace Violence, Asset Protection, Force Protection, Criminal Law, Internal Investigations, Emergency Management, Criminal Investigations, Personnel Security, Counterterrorism, Interrogation, Crisis Management, Protection, Crime Prevention, Background Checks, Close Protection
Interests:
Writing
Spending Time With Family
Security
Law Enforcement
Reading
Camping
Helping People
Fishing
Languages:
English
Spanish
Russell Nielsen Photo 32

Information Security Analyst

Location:
Boise, ID
Industry:
Transportation/Trucking/Railroad
Work:
Primary Health Medical Group Apr 2019 - Jul 2019
System Administrator Truckstop.com Apr 2019 - Jul 2019
Information Security Analyst Debt Reduction Services Inc. Oct 2013 - Sep 2018
It Security Manager Itt Technical Institute Jun 2016 - Sep 2016
Adjunct Professor Directv Nov 2009 - Oct 2013
Customer Service Representative Target Oct 2007 - Sep 2009
Team Leader Sam Goody Oct 2000 - Sep 2007
Store Manager
Education:
Itt Technical Institute - Harrisburg 2016
Bachelors, Bachelor of Science, Information Systems, Cybersecurity Itt Technical Institute 2012 - 2014
Associates
Skills:
Troubleshooting, Technical Support, Windows, Windows Server, Security, Customer Service, Active Directory, Vmware, Windows 7, Windows Xp, Operating Systems, Network Security, Computer Hardware, Call Centers, Microsoft Excel, Servers, Hardware, Networking, Information Technology, System Administration, Information Security, Disaster Recovery, Network Administration, Microsoft Office, Leadership
Certifications:
Microsoft Certified Professional
Microsoft Technology Associate
Microsoft Certified Solutions Associate
Comptia A+ Ce
Comptia Security+ Ce
License E786-9590
License E786-9589
License E828-7530
License Tzj1Wmhkd1Qq1Pqq
Russell Nielsen Photo 33

Russell Nielsen

Russell Nielsen Photo 34

Russell Nielsen - Boise, ID

Work:
Debt Reduction Services Nov 2009 to 2000
IT Specialist DIRECTV - Boise, ID Oct 2013 to Oct 2013
Customer Care Agent Target - Boise, ID Sep 2006 to Sep 2009
Team Leader Musicland - Boise, ID Oct 2007 to Oct 2007
Store Manager Suncoast - Boise, ID Oct 2001 to Oct 2001
Assistant Store Manager
Education:
ITT Tech - Boise, ID 2012 to 2014
Associates in Network Systems Administration
Skills:
Active Directory, Exchange, Windows Server 2008, Windows Server 2012, Microsoft Office 2010, DNS Server

Publications & IP owners

Us Patents

Integrated Circuit Fabrication

US Patent:
7648919, Jan 19, 2010
Filed:
Apr 20, 2006
Appl. No.:
11/407429
Inventors:
Luan C. Tran - Meridian ID, US
John Lee - Boise ID, US
Zengtao “Tony” Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438738, 438401, 438947, 257E21023
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
7776683, Aug 17, 2010
Filed:
May 13, 2008
Appl. No.:
12/119831
Inventors:
Luan C. Tran - Meridian ID, US
John Lee - Boise ID, US
Zengtao “Tony” Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/8242
US Classification:
438241, 438258, 438270, 438626, 438631, 438669, 257758, 257760, 257765, 257E21038
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
8158476, Apr 17, 2012
Filed:
Aug 4, 2010
Appl. No.:
12/850511
Inventors:
Luan C. Tran - Meridian ID, US
John Lee - Boise ID, US
Zengtao “Tony” Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/8242
US Classification:
438241, 438242, 438258, 438637, 438671, 438689, 257758, 257760, 257765, 257E21024
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
8507341, Aug 13, 2013
Filed:
Apr 12, 2012
Appl. No.:
13/445797
Inventors:
Luan C. Tran - Meridian ID, US
John Lee - Boise ID, US
Zengtao “Tony” Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/8242
US Classification:
438241, 438267, 438286, 438296, 438618, 438622, 257E21023
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
2006021, Sep 28, 2006
Filed:
Aug 31, 2005
Appl. No.:
11/216477
Inventors:
Luan Tran - Meridian ID, US
John Lee - Boise ID, US
Zengtao Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
International Classification:
H01L 21/4763
H01L 21/302
H01L 21/44
US Classification:
438622000, 438637000, 438671000, 438738000, 438631000
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
2013032, Dec 5, 2013
Filed:
Aug 8, 2013
Appl. No.:
13/962208
Inventors:
John Lee - Boise ID, US
Zengtao Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 23/544
US Classification:
257773
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
2016000, Jan 7, 2016
Filed:
Sep 16, 2015
Appl. No.:
14/855845
Inventors:
- Boise ID, US
John Lee - Boise ID, US
Zengtao Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
International Classification:
H01L 21/033
H01L 21/306
H01L 27/105
H01L 21/768
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Integrated Circuit Fabrication

US Patent:
2015000, Jan 1, 2015
Filed:
Sep 15, 2014
Appl. No.:
14/486890
Inventors:
- Boise ID, US
John Lee - Boise ID, US
Zengtao Liu - Boise ID, US
Eric Freeman - Kuna ID, US
Russell Nielsen - Boise ID, US
International Classification:
H01L 21/768
H01L 21/306
H01L 21/308
H01L 21/033
US Classification:
438675, 438689, 438703
Abstract:
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Possible Relatives

David L Nielsen  Dawn E Nielsen  Dean E Nielsen  Debbie A Nielsen  Debi W Nielsen  Deborah A Nielsen  Daniel S Nielsen  Russell J Stanford  Russell E White  Russell E Staples 

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