Ryo J Inoue, Age 628903 Feather Hill Rd, Austin, TX 78737

6681273, Jan 20, 2004

Aug 31, 2000

09/652685

Michael Allen - Austin TX
Tim Landreth - Hopkinton MA
Ryo Inoue - Austin TX
Ravi Pratap Singh - Austin TX

Analog Devices, Inc. - Norwood MA

G06F 1300

710 52, 710 4, 710 20, 710 33, 710 36, 710 56, 710310

Methods and apparatus are provided for transferring data words from a source to a destination. The apparatus includes a datapath buffer coupled by a first data bus to the source and coupled by a second data bus to the destination, write control logic for writing a first number of data words in the datapath buffer in response to a first source transfer condition and for writing a second number of data words in the datapath buffer in response to a second source transfer condition, and read control logic for reading the first number of data words from the datapath buffer in response to a first destination transfer condition and for reading the second number of data words from the datapath buffer in response to a second destination transfer condition.

6728870, Apr 27, 2004

Oct 6, 2000

09/680894

Charles P. Roth - Austin TX
Ravi P. Singh - Austin TX
Gregory A. Overkamp - Austin TX
Ryo Inoue - Austin TX

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood CA

G06F 9315

712225, 712216, 712226, 712234

In one embodiment, a programmable processor is adapted to conditionally move data between a pointer register and a data register in response to a single machine instruction. The processor has a plurality of pipelines. In response to the machine instruction, a control unit directs the pipelines to forward the data across the pipelines in order to move the data between the registers.

6760830, Jul 6, 2004

Dec 29, 2000

09/751507

Ryo Inoue - Austin TX
Ravi Kolagotla - Austin TX
Raghavan Sudhakar - Austin TX

Intel Corporation - Santa Clara CA
Analog Devices Inc. - Norwood MA

G06F 1200

711220, 711219

In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+MB, a second corrected target module address when I+M =B+L and an uncorrected module address when B=I+MB+L.

6889316, May 3, 2005

Mar 28, 2001

09/820570

Ryo Inoue - Austin TX, US
Gregory A. Overkamp - Austin TX, US

Intel Corporation - Santa Clara CA
Analog Devices - Norwood MA

G06F009/38

712218, 712219

In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i. e. , a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.

6898695, May 24, 2005

Mar 28, 2001

09/820514

William C. Anderson - Austin TX, US
Ryo Inoue - Austin TX, US

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

G06F009/00

712218, 712219

In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

7065636, Jun 20, 2006

Dec 20, 2000

09/745104

Ryo Inoue - Austin TX, US
Ravi P. Singh - Austin TX, US
Charles P. Roth - Austin TX, US
Gregory A. Overkamp - Austin TX, US

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

G06F 9/50
G06F 9/54

712241, 712218, 712235

In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

7124285, Oct 17, 2006

Mar 29, 2001

09/823276

Ryo Inoue - Austin TX, US
Juan G. Revilla - Austin TX, US

Intel Corporation - Santa Clara CA
Analog Devices, Inc. - Norwood MA

G06F 15/00

712228

In one implementation, a programmable processor is adapted to include a first set of registers and a second set of registers. The first set of registers may have a future file, and the second set of registers may be architectural registers. Following a termination of an instruction in the processor, the future file may be restored with values in the second set of registers. The future file is restored over more than one clock cycle.