Sammy S Cheung, Age 57Hillsborough, CA

6489817, Dec 3, 2002

Sep 26, 2001

09/965290

Choong Kit Wong - Penang, MY
Sammy Cheung - Pleasanton CA
Boon Jin Ang - Penang, MY

Altera Corporation - San Jose CA

H03K 2100

327115, 327117

A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.

6599764, Jul 29, 2003

May 30, 2001

09/870354

Boon Jin Ang - Penang, MY
Sammy Cheung - Pleasanton CA
Kar Keng Chua - Penang, MY

Altera Corporation - San Jose CA

H01L 2166

438 15, 438 17, 324765, 257725

A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

7243329, Jul 10, 2007

Jul 2, 2004

10/884460

Kar Keng Chua - Penang, MY
Sammy Cheung - South San Francisco CA, US

Altera Corporation - San Jose CA

G06F 17/50
G06F 7/38
H01L 25/00

716 16, 716 17, 716 18, 326 39, 326 41

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

7870513, Jan 11, 2011

May 7, 2007

11/801082

Kar Keng Chua - Penang, MY
Sammy Cheung - South San Francisco CA, US
Hee Kong Phoon - Perak, MY
Kim Pin Tan - Penang, MY
Wei Lian Goay - Penang, MY

Altera Corporation - San Jose CA

G06F 17/50
H03K 19/173
H03K 19/177

716 1, 326 38, 326 39, 326 41, 716 16

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

8291355, Oct 16, 2012

Dec 14, 2010

12/967851

Kar Keng Chua - Penang, MY
Sammy Cheung - South San Francisco CA, US
Hee Kong Phoon - Perak, MY
Kim Pin Tan - Penang, MY
Wei Lian Goay - Penang, MY

Altera Corporation - San Jose CA

G06F 17/50

716100, 716101, 716116, 716117, 716121, 716128

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

8504963, Aug 6, 2013

Sep 13, 2012

13/614819

Kar Keng Chua - Penang, MY
Sammy Cheung - South San Francisco CA, US
Hee Kong Phoon - Perak, MY
Kim Pin Tan - Penang, MY
Wei Lian Goay - Penang, MY

Altera Corporation - San Jose CA

G06F 17/50

716116, 716104, 716117

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

2013031, Nov 28, 2013

Jul 31, 2013

13/955200

Sammy Cheung - South San Francisco CA, US
Hee Kong Phoon - Perak, MY
Kim Pin Tan - Penang, MY
Wei Lian Goay - Penang, MY

Altera Corporation - San Jose CA

H03K 19/177

326 38

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

6281704, Aug 28, 2001

Mar 15, 2001

9/810116

Tony Ngai - Campbell CA
Sammy Cheung - Pleasanton CA
Rakesh Patel - Cupertino CA
Vinson Chan - San Jose CA

Altera Corporation - San Jose CA

H03K 19177

326 41

Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e. g. , 405, 720) so the parasitic coupling capacitances (e. g. , 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.