Sandeep A Aji, Age 56Santa Clara, CA

6480996, Nov 12, 2002

Jul 6, 2000

09/610746

Sandeep A. Aji - San Jose CA
Shantanu Ganguly - Austin TX
John Paz - Santa Clara CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1750

716 12, 716 13

An automatic and parameterized compute implemented method for transposing wires in an integrated circuit design can y bus lines with similar impedances, and therefore similar signal transmission characteristics. Using a specially designed CAD tool, a user can specify a transposing porn, intervals at which to transpose wires, and a metal layer through which to accomplish the transposing in the integrated circuit. Using a routing database the tool then automatically determines the locations in the design where transposing needs to be performed, re-routes the wires being transposed while optimizing the circuit design space being used, and re-routes (or causes the re-route of) any other wires affected by the transposing process. The result is a new version of the routing database reflecting transposition, but with no change to the circuits netlist.

7137097, Nov 14, 2006

Jun 25, 2004

10/877259

Sandeep A. Aji - San Francisco CA, US
Ankur Narang - New Delhi, IN
Shantanu Ganguly - Austin TX, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 12, 716 7, 716 8, 716 13

A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

2004004, Mar 4, 2004

Aug 27, 2002

10/228540

Sandeep Aji - San Francisco CA, US
Ankur Narang - New Delhi, IN
Shantanu Ganguly - Austin TX, US

G06F017/50

716/013000, 716/007000

A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

5831867, Nov 3, 1998

Jun 24, 1996

8/669627

Sandeep A. Aji - San Francisco CA
Meera Kasinathan - Sunnyvale CA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1700

364489

An automated method and system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated is disclosed. The automated method and system checks conductive traces, vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations. The operation and effectiveness of the automated method and system are far superior to conventional manual approaches.

5623420, Apr 22, 1997

Nov 16, 1994

8/340706

Clayton L. Yee - San Francisco CA
Sandeep Aji - San Francisco CA
Stefan Rusu - Sunnyvale CA

Sun Microsystems, Inc. - Mountain View CA

G06F 1750

364490

A method and apparatus to distribute spare cells into a standard cell region of an integrated circuit is described. An initial layout of standard cells is first generated by a place and route tool. Afterwards, the initial layout is processed by a spare cell distribution mechanism that simultaneously processes a directive file. The spare cell distribution mechanism distributes, according to a predefined criteria, a preselected cluster of spare cells within the initial layout of standard cells. This processing results in an optimal distribution of spare standard cells within the standard cell region of the semiconductor. The spare cell distribution mechanism also inserts vertical wire terminators into the standard cell region to promote vertical routing, and thus shorter routing paths. In addition, the spare cell distribution mechanism inserts ground connectors and power connectors in the standard cell region to generate a ground and power paths. The outputs of the inserted spare cells may be connected to the ground and power paths until they are subsequently re-routed to correct logic defects in the standard cell region.

5963729, Oct 5, 1999

Jun 26, 1997

8/882986

Sandeep A. Aji - San Francisco CA
Manjunath Doreswamy - Sunnyvale CA
Georgios Konstadinidis - Sunnyvale CA

Sun Microsystems Inc. - Palo Alto CA

G06F 1750

39550006

An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

6072945, Jun 6, 2000

Jun 26, 1997

8/883547

Sandeep A. Aji - San Francisco CA
Manjunath Doreswamy - Sunnyvale CA
Georgios Konstadinidis - Sunnyvale CA

Sun Microsystems Inc. - Palo Alto CA

G06F 1750

39550006

An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.