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Satish Kumar Bansal, Age 641757 Pinewood Ct, Milpitas, CA 95035

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Known as:
Satish K Bansal Satish K Bansel Satish E Satish L
Related to:
Nidhi Bansal

Satish Bansal Phones & Addresses

1757 Pinewood Ct, Milpitas, CA 95035 (408) 946-1458

Santa Clara, CA

Pleasanton, CA

1757 Pinewood Ct, Milpitas, CA 95035 (408) 497-9108

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Satish Kumar Bansal

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Work

Company: Crocus technology Nov 2015 Position: Senior director engineering operations

Education

Degree: Masters School / High School: Northwestern Polytechnic University 1991 to 1992 Specialities: Electronics Engineering

Skills

Semiconductors • Ic • Semiconductor Industry • Soc • Asic • Mixed Signal • Analog • Cmos • Silicon • Failure Analysis • Flash Memory • Product Management • Integrated Circuits • Product Development • Program Management • Product Marketing • Start Ups • Application Specific Integrated Circuits • Electronics • System on A Chip

Languages

English • Hindi • Punjabi

Industries

Semiconductors

Mentions for Satish Kumar Bansal

Satish Bansal resumes & CV records

Resumes

Satish Bansal Photo 25

Senior Director Engineering Operations

Location:
Milpitas, CA
Industry:
Semiconductors
Work:
Crocus Technology
Senior Director Engineering Operations Crocus Technology
Director Product and Test Engineering Sst
Director Product and Test Engineering Atmel Corporation 1989 - 1997
Product Engineer
Education:
Northwestern Polytechnic University 1991 - 1992
Masters, Electronics Engineering Thapar Institute of Engineering & Technology 1979 - 1983
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Semiconductors, Ic, Semiconductor Industry, Soc, Asic, Mixed Signal, Analog, Cmos, Silicon, Failure Analysis, Flash Memory, Product Management, Integrated Circuits, Product Development, Program Management, Product Marketing, Start Ups, Application Specific Integrated Circuits, Electronics, System on A Chip
Languages:
English
Hindi
Punjabi

Publications & IP owners

Us Patents

Method Of Testing Data Retention Of A Non-Volatile Memory Cell Having A Floating Gate

US Patent:
2013011, May 9, 2013
Filed:
Nov 9, 2011
Appl. No.:
13/293056
Inventors:
Viktor Markov - Sunnyvale CA, US
Jong-Won Yoo - Cupertino CA, US
Satish Bansal - Milpitas CA, US
Alexander Kotov - Sunnyvale CA, US
International Classification:
G11C 16/04
US Classification:
3651853, 36518518
Abstract:
A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.

Possible Relatives

Krishan M Bansal  Seema Bansal  Shashi T Bansal  Shruti Bansal  Anita Bansal  Anuj Bansal  Anurag Bansal  Satish Kumar  Satish K Reddy  Satish B Rao 

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