Sheldon Jay Meyers, Age 5884 Mann Blvd, Halfmoon, NY 12065

Sheldon Meyers Phones & Addresses

84 Mann Blvd, Clifton Park, NY 12065 (518) 280-6319

Halfmoon, NY

Williamsville, NY

Wappingers Falls, NY

Cheektowaga, NY

Phoenix, AZ

Wappingers Fl, NY

84 Mann Blvd, Clifton Park, NY 12065

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Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Mentions for Sheldon Jay Meyers

Publications & IP owners

Us Patents

Radial Lithographic Source Homogenizer

US Patent:
2020002, Jan 16, 2020
Filed:
Jul 10, 2018
Appl. No.:
16/031767
Inventors:
- Grand Cayman, KY
Sheldon J. Meyers - Halfmoon NY, US
International Classification:
G21K 1/04
H05G 2/00
G21K 1/06
G03F 7/20
Abstract:
A method includes identifying a contamination region of a collector in a light source, positioning a subset of a plurality of movable light-blocking elements around a periphery of a circular aperture of the light source to compensate for the contamination region, and transmitting light from the light source through the circular aperture.

Uniformity Control Of Metal-Based Photoresists

US Patent:
2019021, Jul 11, 2019
Filed:
Jan 11, 2018
Appl. No.:
15/867854
Inventors:
- Grand Cayman, KY
Erik Robert HOSLER - Cohoes NY, US
Sheldon MEYERS - Halfmoon NY, US
Scott KENNY - Ballston Lake NY, US
Assignee:
GLOBALFOUNDRIES INC. - GRAND CAYMAN
International Classification:
G03F 7/16
B05D 3/00
B05D 1/00
B05B 3/02
G03F 7/20
Abstract:
An EUV photoresist composition includes paramagnetic particles that are adapted to block EUV radiation. The magnetic manipulation of the paramagnetic particles within a deposited layer of EUV photoresist can beneficially impact focus control and the achievable line width roughness during subsequent photolithographic processing. A spin-coating apparatus for dispensing the EUV photoresist composition onto a substrate includes a plurality of concentric electromagnets located beneath the substrate that influence the distribution of the paramagnetic particles in the photoresist layer.

Semiconductor Substrates And Methods For Processing Semiconductor Substrates

US Patent:
2017001, Jan 19, 2017
Filed:
Jul 14, 2015
Appl. No.:
14/798796
Inventors:
- Grand Cayman, KY
Sandeep Gaan - Clifton Park NY, US
Sheldon Meyers - Clifton Park NY, US
Nisha Pillai - Malta NY, US
Edmund Kenneth Banghart - Pittsford NY, US
Kyle Jung - Saratoga Springs NY, US
International Classification:
H01L 21/02
H01L 29/16
Abstract:
Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

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