Sherif S Abdalla, Age 54Laguna Beach, CA

Sherif Abdalla Phones & Addresses

Laguna Beach, CA

2177 Corte Arboles, Carlsbad, CA 92009 (760) 479-0970

2882 Rancho Cortes, Carlsbad, CA 92009 (760) 479-0970

Burlington, VT

Oceanside, CA

San Diego, CA

Mentions for Sherif S Abdalla

Career records & work history

Medicine Doctors

Sherif G. Nour Abdalla

Specialties:
Diagnostic Radiology
Work:
Emory ClinicEmory University Hospital Radiology
1364 Clifton Rd NE, Atlanta, GA 30322
(404) 778-2650 (phone) (404) 778-2145 (fax)
Site
Education:
Medical School
Univ of Cairo, Fac of Med, Cairo, Egypt (330 02 Prior 1/71)
Graduated: 1992
Languages:
English
Description:
Dr. Nour Abdalla graduated from the Univ of Cairo, Fac of Med, Cairo, Egypt (330 02 Prior 1/71) in 1992. He works in Atlanta, GA and specializes in Diagnostic Radiology. Dr. Nour Abdalla is affiliated with Emory Johns Creek Hospital, Emory University Hospital and Emory University Hospital Midtown.

Resumes & CV records

Resumes

Sherif Abdalla Photo 28

Director, R And D

Location:
2882 Rancho Cortes, Carlsbad, CA 92009
Industry:
Semiconductors
Work:
Broadcom - Irvine since Aug 2013
Sr. Manager Engineering
Broadcom - Irvine Apr 2012 - Jul 2013
Multiple Positions
Luxtera Inc. - Carlsbad, CA Jun 2005 - Mar 2012
Sr. Director, Engineering
Snowbush Inc. 2002 - 2005
Staff Engineer
Zomina Ltd 1997 - 1998
President and Founder
Schlumberger 1992 - 1996
GFE
Education:
University of Toronto 1999 - 2002
M.A.Sc., Electrical and Computer Engineering
Cairo University 1987 - 1992
B.Sc., Electrical and Communication Engineering
Skills:
Mixed Signal, Ic, Analog, Semiconductors, Serdes, Electronics, Integrated Circuit Design, Asic, Silicon, Pll, Cmos, Soc, Product Development, Program Management, Analog Circuit Design, Embedded Systems, Testing, Firmware, Engineering Management, Circuit Design, Simulations, Engineering, Electrical Engineering, Vco, Rf, Pcb Design, Semiconductor Industry, Fpga, Eda, Application Specific Integrated Circuits, Integrated Circuits, Design For Manufacturing, Hardware Architecture, Simulation, Analog Design
Languages:
English
Sherif Abdalla Photo 29

Sherif Abdalla

Sherif Abdalla Photo 30

Sherif Abdalla

Sherif Abdalla Photo 31

Sherif Abdalla

Publications & IP owners

Us Patents

Method And System For Optoelectronics Transceivers Integrated On A Cmos Chip

US Patent:
2009002, Jan 22, 2009
Filed:
Sep 30, 2008
Appl. No.:
12/241961
Inventors:
Thierry Pinguet - Cardiff-by-the-Sea CA, US
Steffen Gloeckner - San Diego CA, US
Sherif Abdalla - Carlsbad CA, US
Sina Mirsaidi - San Diego CA, US
Peter De Dobbelaere - San Diego CA, US
International Classification:
H04B 10/00
US Classification:
398164
Abstract:
Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.

Method And System For Monolithic Integration Of Photonics And Electronics In Cmos Processes

US Patent:
2010005, Mar 11, 2010
Filed:
Sep 4, 2009
Appl. No.:
12/554449
Inventors:
Thierry Pinguet - Cardiff-by-the-Sea CA, US
Steffen Gloeckner - San Diego CA, US
Peter De Dobbelaere - San Diego CA, US
Sherif Abdalla - Carlsbad CA, US
Daniel Kucharski - Carlsbad CA, US
Gianlorenzo Masini - Carlsbad CA, US
Kosei Yokoyama - San Diego CA, US
John Guckenberger - San Diego CA, US
Attila Mekis - Carlsbad CA, US
International Classification:
H01L 27/12
H01L 21/782
US Classification:
257351, 438481, 257E27112, 257E217
Abstract:
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Method And Circuit For Encoding Multi-Level Pulse Amplitude Modulated Signals Using Integrated Optoelectronic Devices

US Patent:
2010006, Mar 11, 2010
Filed:
Sep 8, 2009
Appl. No.:
12/555291
Inventors:
Daniel Kucharski - Carlsbad CA, US
Sherif Abdalla - Carlsbad CA, US
Brian Welch - San Diego CA, US
International Classification:
G02F 1/21
G02F 1/01
US Classification:
359290, 359238
Abstract:
Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more electrical input signals. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate, which may include one of: silicon, gallium arsenide, germanium, indium gallium arsenide, polymers, or indium phosphide. The optical modulator may include a Mach-Zehnder interferometer or one or more ring modulators.

Method And System For Implementing High-Speed Interfaces Between Semiconductor Dies In Optical Communication Systems

US Patent:
2011020, Aug 25, 2011
Filed:
Feb 23, 2011
Appl. No.:
13/033439
Inventors:
Daniel Kucharski - San Marcos CA, US
John Andrew Guckenberger - San Diego CA, US
Thierry Pinguet - Cardiff-by-the-Sea CA, US
Sherif Abdalla - Carlsbad CA, US
International Classification:
G02B 6/26
US Classification:
385 39
Abstract:
A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Monolithic Integration Of Photonics And Electronics In Cmos Processes

US Patent:
2012013, May 31, 2012
Filed:
Feb 2, 2012
Appl. No.:
13/364909
Inventors:
Thierry Pinguet - Cardiff-by-the-Sea CA, US
Steffen Gloeckner - San Diego CA, US
Peter De Dobbelaere - San Diego CA, US
Sherif Abdalla - Carlsbad CA, US
Daniel Kucharski - Carlsbad CA, US
Gianlorenzo Masini - Carlsbad CA, US
Kosei Yokoyama - San Diego CA, US
John Guckenberger - San Diego CA, US
Attila Mekis - Carlsbad CA, US
International Classification:
H01L 27/12
H01L 21/782
US Classification:
257351, 438481, 257E217, 257E27112
Abstract:
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Monolithic Integration Of Photonics And Electronics In Cmos Processes

US Patent:
2012013, May 31, 2012
Filed:
Feb 2, 2012
Appl. No.:
13/364845
Inventors:
Thierry Pinguet - Cardiff-by-the-Sea CA, US
Steffen Gloeckner - San Diego CA, US
Peter De Dobbelaere - San Diego CA, US
Sherif Abdalla - Carlsbad CA, US
Daniel Kucharski - Carlsbad CA, US
Gianlorenzo Masini - Carlsbad CA, US
Kosei Yokoyama - San Diego CA, US
Guckenberger John - San Diego CA, US
Attila Mekis - Carlsbad CA, US
International Classification:
H01L 21/50
US Classification:
438107, 257E21499
Abstract:
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Method And System For Hybrid Integration Of Optical Communication Systems

US Patent:
2012030, Nov 29, 2012
Filed:
Aug 7, 2012
Appl. No.:
13/568406
Inventors:
Thierry Pinguet - Vashon WA, US
Sherif Abdalla - Carlsbad CA, US
Mark Peterson - San Diego CA, US
Gianlorenzo Masini - Carlsbad CA, US
Peter DeDobbelaere - San Diego CA, US
International Classification:
H04B 10/02
US Classification:
398115
Abstract:
Methods and systems for hybrid integration of optical communication systems are disclosed and may include receiving continuous wave (CW) optical signals in a silicon photonics die (SPD) from an optical source external to the SPD. The received CW optical signals may be processed based on electrical signals received from an electronics die bonded to the SPD via metal interconnects. Modulated optical signals may be received in the SPD from optical fibers coupled to the SPD. Electrical signals may be generated in the SPD based on the received modulated optical signals and communicated to the electronics die via the metal interconnects. The CW optical signals may be received from an optical source assembly coupled to the SPD and/or from one or more optical fibers coupled to the SPD. The received CW optical signals may be processed utilizing one or more optical modulators, which may comprise Mach-Zehnder interferometer modulators.

Method And System For Encoding Multi-Level Pulse Amplitude Modulated Signals Using Integrated Optoelectronic Devices

US Patent:
2012031, Dec 13, 2012
Filed:
Aug 7, 2012
Appl. No.:
13/568616
Inventors:
Daniel Kucharski - Carlsbad CA, US
Brian Welch - San Diego CA, US
Sherif Abdalla - Carlsbad CA, US
International Classification:
H04B 10/04
US Classification:
398 43, 398186
Abstract:
Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more electrical input signals. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers. Phase addition may be synchronized utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate, which may include one of: silicon, gallium arsenide, germanium, indium gallium arsenide, polymers, or indium phosphide. The optical modulator may include a Mach-Zehnder interferometer or one or more ring modulators.

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