Siamak Te Arya, Age 7221310 Columbus Ave, Cupertino, CA 95014

6360313, Mar 19, 2002

Sep 8, 2000

09/657758

Howard G. Sachs - Los Altos CA
Siamak Arya - Cupertino CA

Intergraph Corporation - Huntsville AL

G06F 938

712215, 712 24, 712207, 712213, 712234

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

6892293, May 10, 2005

Apr 9, 1998

09/057861

Howard G. Sachs - Los Altos CA, US
Siamak Arya - Cupertino CA, US

Intergraph Corporation - Huntsville AL

G06F009/38

712215, 712 24, 712206

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

7039791, May 2, 2006

Jul 3, 2002

10/189214

Howard G. Sachs - Los Altos CA, US
Siamak Arya - Palo Alto CA, US

Intergraph Corporation - Huntsville AL

G06F 9/30

712215, 712 24, 712206

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

7724568, May 25, 2010

Feb 29, 2008

12/040707

Siamak Arya - Cupertino CA, US
Fong-Long Lin - Fremont CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 16/04

36518502, 36518508, 3651892

A memory device comprises a non-volatile electrically alterable memory which is susceptible to read disturbance. The device has a control circuit for controlling the operation of the non-volatile memory. The device further has a first volatile cache memory. The first volatile cache memory is connected to the control circuit and is for storing data to be written to or read from the non-volatile memory, as cache for the memory device. The device further has a second volatile cache memory. The second volatile cache memory is connected to the control circuit and is for storing data read from the non-volatile memory as read cache for the memory device. Finally the control circuit reads data from the second volatile cache memory in the event of a data miss from the first volatile cache memory, and reads data from the non-volatile memory in the event of a data miss from the first and second volatile cache memories.

2009015, Jun 18, 2009

Dec 12, 2007

11/954577

Siamak Arya - Cupertino CA, US

G06F 12/06
G06F 13/28

711103, 711E12083, 711E12008

In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency.

2010008, Apr 8, 2010

Oct 6, 2008

12/246327

Siamak Arya - Cupertino CA, US
Fong-Long Lin - Fremont CA, US

G06F 12/02

711103, 711E12008

A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time.

2010012, May 20, 2010

Nov 17, 2008

12/272710

Siamak Arya - Cupertino CA, US
Fong-Long Lin - Fremont CA, US

G06F 9/455
G06F 12/00

703 26, 711104, 711E12001

A NOR emulating memory device has a memory controller with a first bus for receiving a NOR command signal, and for servicing a read operation from a desired address in a NOR memory. The memory controller has a second bus for communicating with a NAND memory in a NAND memory protocol, and a third bus for communicating with a RAM memory. A NAND memory is connected to the second bus. The NAND memory has an array of memory cells divided into a plurality of pages with each page divided into a plurality of sectors, with each sector having a plurality of bits. The NAND memory further has a page buffer for storing a page of bits read from the array during the read operation of the NAND memory. A RAM memory is connected to the third bus. The memory controller has a NOR memory for storing program code for initiating the operation of the memory controller, and for receiving NOR commands from the first bus and issuing NAND protocol commands on the second bus, in response thereto, to emulate the operation of a NOR memory device. The program code causes the memory controller to read a first sector of bits from the page buffer of the NAND memory and to write the sector of bits into the RAM memory, wherein the first sector contains the location of the desired address, and supplying data from said RAM memory in response to the read operation.

2010031, Dec 9, 2010

Jun 3, 2009

12/477799

Siamak Arya - Cupertino CA, US
Fong-Long Lin - Fremont CA, US
Thao Thach Tran - Fremont CA, US

G06F 3/00
H04B 7/005

710 51, 370278

A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch.