Simon Pang resumes & CV records
Resumes
Simon Pang
Location:
San Diego, CA
Industry:
Semiconductors
Simon Pang
Simon Pang9625 Caminito Tizona, San Diego, CA 92126
Simon Pang Phones & Addresses
9625 Caminito Tizona, San Diego, CA 92126 (858) 530-8213
11336 Camino Playa Cancun U, San Diego, CA 92124
Mentions for Simon Pang
Publications & IP owners
Us Patents
Integrated Circuit Template Cell System And Method
US Patent:
6502231, Dec 31, 2002
Filed:
May 31, 2001
Appl. No.:
09/871473
Inventors:
Simon S. Pang - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 1750
US Classification:
716 17, 716 14
Abstract:
A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.
Integrated Circuit Template Cell System And Method
US Patent:
6725443, Apr 20, 2004
Filed:
Oct 24, 2002
Appl. No.:
10/280978
Inventors:
Simon S. Pang - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA
Rimon Shookhtim - Cardiff by the Sea CA
Joseph J. Balardeta - Carlsbad CA
Gary Wong - San Diego CA
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 1750
US Classification:
716 17, 716 14
Abstract:
A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.
Signal Routing In A Node Of A 1:N Automatic Protection Switching Network
US Patent:
7327672, Feb 5, 2008
Filed:
Jan 31, 2003
Appl. No.:
10/356167
Inventors:
Simon S. Pang - San Diego CA, US
Joseph J. Balardeta - Carlsbad CA, US
Joseph J. Balardeta - Carlsbad CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
G06F 11/00
US Classification:
370228, 370217, 714 4
Abstract:
Automatic protection switching is implemented by channel devices in a data communication system node. Each channel devices includes input and output ports, a data receive port, a data send port, and a signal routing arrangement controlled by a processor element. The signal routing arrangement routes data between the channel devices such that, in the event of a channel failure, one channel device functions as a protection channel device. In a normal operating mode, each channel device routes data from its data receive port to its data send port, and routes data from its input port to its output port. In a protection mode, the protection channel device (and the protected channel device) routes data from its data receive port to its output port, and routes data from its input port to its data send port, while the remaining working channel devices function in the normal operating mode.
Selectable Loss Of Signal (Los) Criteria
US Patent:
7633878, Dec 15, 2009
Filed:
Sep 7, 2006
Appl. No.:
11/516899
Inventors:
Timothy Eric Giorgetta - San Diego CA, US
Madjid A. Hamidi - San Diego CA, US
Simon Sai-Man Pang - La Mesa CA, US
Madjid A. Hamidi - San Diego CA, US
Simon Sai-Man Pang - La Mesa CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H04J 1/16
US Classification:
370244, 370252
Abstract:
A system and method are provided for selecting loss of signal (LOS) criteria in a serial communications receiver. The method receives a serial stream of digital data and selects LOS criteria. The serial stream of digital data is compared to the selected LOS criteria. In response to the serial stream of digital data failing to meet the selected LOS criteria, a LOS signal is generated. Some examples of the LOS criteria that might be selected include: a “signal detect” signal received from the source transmitting the serial stream of digital data, a run length test, a signal strength (voltage amplitude) test, harmonic band detection test, and a received data clock test. In one aspect, selecting LOS criteria includes selecting combinations of the above-mentioned LOS criteria, so that the LOS signal is generated in response to failing to meet the combination of selected LOS criteria.
System And Method For Automatic Clock Frequency Acquisition
US Patent:
7720189, May 18, 2010
Filed:
Nov 9, 2006
Appl. No.:
11/595012
Inventors:
Viet Linh Do - Carlsbad CA, US
Mehmet Mustafa Eker - San Marcos CA, US
Simon Pang - San Diego CA, US
Mehmet Mustafa Eker - San Marcos CA, US
Simon Pang - San Diego CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03D 3/24
US Classification:
375376, 331 11
Abstract:
A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref/n, where n is an integer≧1. The count for each sampling frequency is compared to the count for Fref (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref, and the coarse clock frequency is set to Fc =Fref/(x−1).
High Speed Multi-Modulus Prescalar Divider
US Patent:
7826563, Nov 2, 2010
Filed:
Mar 13, 2007
Appl. No.:
11/717262
Inventors:
Hongming An - San Diego CA, US
Simon Pang - San Diego CA, US
Viet Linh Do - Carlsbad CA, US
Simon Pang - San Diego CA, US
Viet Linh Do - Carlsbad CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03D 3/24
US Classification:
375327, 375219, 375221, 375294, 375302, 375376, 455 6713, 4552761, 331 2, 331 16
Abstract:
A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0. 75, 0. 875, 1, 1. 125, or 1. 25.
False Frequency Lock Detector
US Patent:
7936853, May 3, 2011
Filed:
Nov 9, 2007
Appl. No.:
11/983675
Inventors:
Simon Pang - San Diego CA, US
Viet Linh Do - Carlsbad CA, US
Mehmet Mustafa Eker - San Marcos CA, US
Viet Linh Do - Carlsbad CA, US
Mehmet Mustafa Eker - San Marcos CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H04L 7/00
US Classification:
375354, 331DIG 2, 327141, 327160
Abstract:
A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate—to detect if the clock signal is incorrectly locked to the first rate.
Frequency Pattern Detector
US Patent:
7956649, Jun 7, 2011
Filed:
Jul 26, 2010
Appl. No.:
12/843534
Inventors:
Simon Pang - San Diego CA, US
Viet Do - Carlsbad CA, US
Viet Do - Carlsbad CA, US
Assignee:
Applied Micro Circuits Corporation - San Diego CA
International Classification:
H03D 13/00
US Classification:
327 42, 327 49
Abstract:
A window sampling system and method are provided for comparing a signal with an unknown frequency to a reference clock. A pattern modulator accepts a compClk signal and supplies a test window with a period equal to n compClk periods, where n is an integer greater than 1. A pattern detector accepts the test window and a reference clock, and contrasts the test window with the reference clock. In response to failing to fit n reference clock periods inside the test window, the pattern detector supplies a frequency pattern detector output signal (fpdOut) indicating that the frequency of the compClk is greater than the reference clock frequency.
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