Xiaogang S Zhu, Age 651721 Via Lugano, San Jose, CA 95120

7610439, Oct 27, 2009

Feb 9, 2007

11/673348

Jonathan F. Lee - Dublin CA, US
Xiaogang Zhu - Fremont CA, US

Broadcom Corporation - Irvine CA

G06F 1/04

711103

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

7610456, Oct 27, 2009

Nov 26, 2007

11/945128

Xiaogang Zhu - Fremont CA, US
Jonathan F. Lee - Dublin CA, US

Broadcom Corporation - Irvine CA

G06F 12/00

711156, 711103, 711115, 711154

Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

8176370, May 8, 2012

Sep 13, 2004

10/940146

Jonathan Lee - Dublin CA, US
Xiaogang Zhu - Fremont CA, US
Andrew S. Hwang - Redondo Beach CA, US

Broadcom Corporation - Irvine CA

G11C 29/00

714718, 714744

Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter () its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

8489717, Jul 16, 2013

Sep 24, 2009

12/566581

Vladimir Bronstein - Los Altos CA, US
James Chen - Fremont CA, US
Xiaogang Zhu - San Jose CA, US

Hitachi, Ltd. - Tokyo

G06F 15/177

709222, 709225, 398 45

A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided. The system includes: a memory; and a caching entity configured to monitor transmissions from the provisioning server of the configuration files to the network nodes so as to both store the configurations files in the memory and to pass-through the configuration files to the network nodes; the caching entity being further configured to monitor requests to the provisioning server for respective ones of the DOCSIS configuration files from the network nodes, the caching entity being further configured to determine for each of the requests whether the requested configuration file has been previously requested node such that if the caching entity determines that the requested configuration file has been previously requested the caching entity retrieves the previously requested configuration file from the memory and returns the retrieved-from-memory configuration file to the network node.

2007001, Jan 18, 2007

Jul 14, 2005

11/181547

Xiaogang Zhu - Fremont CA, US
Jonathan Lee - Dublin CA, US

G06F 12/00

711115000, 711103000, 711170000

Automatically detecting types of external FLASH devices is provided, and may comprise communicating one or more read memory device ID commands corresponding to at least one supported memory device to at least one memory device. Data received in response to this communication may be utilized to determine whether the received data identifies the memory device as one of the plurality of supported memory devices. The supported memory devices may be serial FLASH memory devices. Each read memory device ID command may be manufacturer specific, or may be specific to a group of the supported memory devices. The communicating of read memory device ID commands and determining whether the memory device is a supported memory device may be repeated if the memory device is not identified as one of the supported memory devices. There may be a limit to the number of times this is repeated.

2010000, Jan 7, 2010

Sep 14, 2009

12/558803

Jonathan F. Lee - Dublin CA, US
Xiaogang Zhu - Fremont CA, US

G06F 12/02
G06F 1/04

711103, 713500, 711E12008

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

2018028, Oct 4, 2018

Apr 3, 2017

15/477792

- Plano TX, US
Xiaogang Zhu - Santa Clara CA, US
Serhat Nazim Avci - Santa Clara CA, US

G06F 13/42
G06F 13/40
G06F 13/38

A Universal Serial Bus (USB) switch includes a host port and a plurality of USB device ports. Each USB device port is configured to be coupled to a respective plurality of USB devices. A USB interface is coupled to the host port. A switch matrix is coupled between the USB interface and the plurality of USB device ports and is configured to switch the USB interface to one of the plurality of USB device ports. A switch controller is coupled to the plurality of USB interfaces, the host port, and the switch matrix. The switch controller is configured to control operation of the USB switch.

2018022, Aug 9, 2018

Apr 3, 2018

15/944532

- Plano TX, US
Xiaogang Zhu - San Jose CA, US
Masood Mortazavi - San Jose CA, US

Futurewei Technologies, Inc. - Plano TX

G11B 17/22
G11B 17/14
B25J 15/10
B25J 15/08
B25J 15/00
B25J 18/02
G11B 17/16
B25J 15/12
G11B 17/04
G11B 17/038

The present disclosure relates to a storage and transfer apparatus for mass transfer of a plurality of data discs to trays of a plurality stacked disc drives. The storage and transfer apparatus may store a plurality of discs with the disc hold pins retracted and the telescopic sections collapsed over each other. In such a configuration, the stored discs may lie in contact with each other. The storage and transfer apparatus may transfer the plurality of discs to the trays of the plurality of stacked disc drives with the discs holding pins extended and the telescopic sections extended relative to each other.