Sing ChinFremont, CA

Sing Chin Phones & Addresses

Fremont, CA

40340 Strawflower Way, Fremont, CA 94538

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Mentions for Sing Chin

Sing Chin resumes & CV records

Resumes

Sing Chin Photo 19

Sing Chin

Sing Chin Photo 20

Sing Chin

Publications & IP owners

Us Patents

Medical Instrument Positioning Tool And Method

US Patent:
6802840, Oct 12, 2004
Filed:
Jun 1, 2001
Appl. No.:
09/872652
Inventors:
Sing Fatt Chin - Fremont CA
Dany Berube - Fremont CA
Dinesh I. Mody - Pleasanton CA
Nancy Norris - Fremont CA
Assignee:
AFx, Inc. - Santa Clara CA
International Classification:
A61B 1818
US Classification:
606 41, 606 45
Abstract:
A system and method for positioning a medical instrument at a desired biological target tissue site is provided. The system includes an elongated sheath having a deflectable distal end configured to deflect or otherwise position at least a portion of a medical instrument during a surgical procedure allowing for the placement of the deflected portion adjacent or proximate to a predetermined target tissue surface. The positioning system may be incorporated into the medical instrument. The medical instrument may be an ablation system.

Pipeline Adc Using Multiplying Dac And Analog Delay Circuits

US Patent:
7187318, Mar 6, 2007
Filed:
Aug 8, 2005
Appl. No.:
11/198970
Inventors:
Bumha Lee - Pleasanton CA, US
Sing W. Chin - Alameda CA, US
Bill C. Wong - Milpitas CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03M 1/38
US Classification:
341161, 341155, 341122
Abstract:
Each stage of a pipeline ADC includes an analog delay cell, a sub-stage ADC, and a multiplying digital-to-analog converter (MDAC). The MDAC includes a sample-and-hold amplifier (SHA) circuit, a summer, a gain stage, and a DAC. The MDAC is arranged in cooperation with the analog delay cell such that the effects of a long comparator decision time under high-speed conditions are minimized. The first SHA, half clock cycle delay cell with unity gain transfer function, samples the input signal during the first clock period, followed by a strobe of the sub-ADC. Substantially half of the clock period can be utilized for the comparison time of the sub-ADC using the described methods. Since decoding is completed before MDAC sampling the first SHA output so that the complete half clock cycle can be arranged for amplifier settling in order to achieve the maximum operating speed with a given amplifier bandwidth.

Method Of Positioning A Medical Instrument

US Patent:
7303560, Dec 4, 2007
Filed:
Sep 24, 2004
Appl. No.:
10/949014
Inventors:
Sing Fatt Chin - Fremont CA, US
Dany Berube - Fremont CA, US
Dinesh I. Mody - Pleasanton CA, US
Nancy Norris - Fremont CA, US
Assignee:
AFx, Inc. - Santa Clara CA
International Classification:
A61B 18/18
A61M 25/06
US Classification:
606 41, 606 45, 604528, 600146
Abstract:
A system and method for positioning a medical instrument at a desired biological target tissue site is provided. The system includes an elongated sheath having a deflectable distal end configured to deflect or otherwise position at least a portion of a medical instrument during a surgical procedure allowing for the placement of the deflected portion adjacent or proximate to a predetermined target tissue surface. The positioning system may be incorporated into the medical instrument. The medical instrument may be an ablation system.

Duty Cycle Stabilizer

US Patent:
7432752, Oct 7, 2008
Filed:
Apr 24, 2007
Appl. No.:
11/739594
Inventors:
Bumha Lee - Pleasanton CA, US
Sing W. Chin - Alameda CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 3/017
US Classification:
327175, 327172
Abstract:
A duty cycle stabilizer circuit () receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator () and a pulse width extender circuit (). The pulse generator generates a first clock pulse (V) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer () providing the output clock signal having the first duty cycle, a charge pump () receiving the output clock signal directly and a differential amplifier () generating an output signal for controlling the pulse width of the first and second clock pulses.

Bias Device Clamping Circuit For Fast Over-Range Recovery

US Patent:
7474154, Jan 6, 2009
Filed:
Apr 23, 2007
Appl. No.:
11/738645
Inventors:
Bumha Lee - Pleasanton CA, US
David B. Barkin - San Francisco CA, US
Sing W. Chin - Alameda CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03F 3/45
US Classification:
330260
Abstract:
A gain-boosted telescopic amplifier () includes clamping circuits for the bias devices to ensure fast over-voltage recovery. In one embodiment, the gain-boosted telescopic amplifier includes an input pair of NMOS transistors (M, M), a pair of NMOS gain-boosted cascode transistors (M, M) and a pair of PMOS gain-boosted cascode transistors (M, M). The amplifier includes first and second clamping circuits driving the gate terminals of the pair of PMOS cascode transistors, respectively. The clamping circuits limit the gate voltage of the PMOS cascode transistors to be within a threshold voltage from the desired bias voltage. Each clamping circuit can include only a pull-down device, a pull-up device or both. In another embodiment, the amplifier includes clamping circuits driving the gate terminals of the pair of NMOS cascode transistors for limiting the gate voltage of the NMOS cascode transistors to be within a threshold voltage of the desired bias voltage.

Fast Settling Reference Voltage Buffer With Wide Reference Range

US Patent:
7639059, Dec 29, 2009
Filed:
Sep 12, 2007
Appl. No.:
11/853827
Inventors:
Hao Yu - Fremont CA, US
Sing Chin - Alameda CA, US
Bill Wong - Milpitas CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 5/00
US Classification:
327333, 327108, 326 81, 365226
Abstract:
A reference voltage buffer circuit () includes first and second transistors (M, M) and first and second resistors (R, R) connected in series between positive and negative power supply voltages and providing a positive reference voltage (Vrp) and a negative reference voltage (Vrn) at the first current handling terminals of the first and second transistors, respectively. A first control voltage (Vg) for driving the first transistor is generated by a first feedback loop and using a positive boosted voltage. A second control voltage (Vg) for driving the second transistor is generated by a second feedback loop and using a negative boosted voltage. The first and second feedback loops establish the first and second control voltages while the positive and negative boosted voltages ensure sufficient drives are provided to the first and second transistors. The reference voltage buffer is capable of fast settling while maintaining a wide reference voltage range.

Duty Cycle Correction Circuit With Small Duty Error And Wide Frequency Range

US Patent:
7705649, Apr 27, 2010
Filed:
Apr 3, 2008
Appl. No.:
12/062426
Inventors:
Hao Yu - Fremont CA, US
Sing W. Chin - Alameda CA, US
Bill C. Wong - Milpitas CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 3/017
US Classification:
327175, 327158
Abstract:
A duty cycle correction circuit () for receiving an input clock signal () and generating an output clock signal () having a predetermined duty cycle includes a clock trigger circuit () generating the output clock signal () having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (); a charge pump circuit () receiving the output clock signal and generating charging and discharging currents for a capacitor (C) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit () receiving the control voltage and generating first and second bias voltages () in response to the control voltage; and a delay-locked loop circuit () receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.

Tissue Ablation System With A Sliding Ablating Device And Method

US Patent:
2003006, Apr 10, 2003
Filed:
Jun 21, 2002
Appl. No.:
10/177840
Inventors:
Sing Chin - Fremont CA, US
Berube Dany - Milpitas CA, US
Dinesh Mody - Pleasanton CA, US
Nancy Norris - Fremont CA, US
Assignee:
AFX, INC. - FREMONT CA
International Classification:
A61B018/14
US Classification:
606/041000
Abstract:
A system and method for ablating a selected portion of a contact surface of biological tissue is provided. The system includes an elongated ablation sheath having a preformed shape adapted to substantially conform a predetermined surface thereof with the contact surface of the tissue. The ablation sheath defines an ablation lumen sized to slideably receive an elongated ablative device longitudinally therethrough. The ablative device includes a flexible ablation element selectively generating an ablative field sufficiently strong to cause tissue ablation. Advancement of the ablation element slideably through the ablation lumen of the ablation sheath selectively places the ablation element along the ablation path for guide ablation on the contact surface when the predetermined surface is in strategic contact therewith. The ablation lumen and the ablative device cooperate to position the ablation element proximate to the ablation sheath predetermined surface for selective ablation of the selected portion within the ablative field.

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.