Stephen P Kornachuk, Age 571656 Castro Dr, Campbell, CA 95008

7586800, Sep 8, 2009

Aug 8, 2007

11/836088

Stephen Kornachuk - San Jose CA, US

Tela Innovations, Inc. - Campbell CA

G11C 7/00
G06F 12/00

365196, 365191, 365194, 711167

A computer memory includes a primary self-timing signal path defined by a model wordline signal path and a model bitline signal pair path. The primary self-timing signal path is defined to generate and transmit a model bitline signal pair. The computer memory also includes a control block defined to receive the model bitline signal pair from the primary self-timing signal path. The control block is defined to sense when a distinctive differential exists between the signals of the model bitline signal pair. The control block is further defined to generate and transmit a sense enable signal to a memory core upon sensing the distinctive differential between the signals of the model bitline signal pair.

8225261, Jul 17, 2012

Mar 7, 2009

12/399948

Joseph Hong - Chandler AZ, US
Stephen Kornachuk - San Jose CA, US
Scott T. Becker - Scotts Valley CA, US

Tela Innovations, Inc. - Los Gatos CA

G06F 17/50

716122, 716119, 716135

First and second virtual grates are defined as respective sets of parallel virtual lines extending across a layout area in first and second perpendicular directions, respectively. The virtual lines of the first and second virtual grates correspond to placement locations for layout features in lower and higher chip levels, respectively. Each intersection point between virtual lines of the first and second virtual grates is a gridpoint within a vertical connection placement grid. Vertical connection structures are placed at a number of gridpoints within the vertical connection placement grid so as to provide electrical connectivity between layout features in the lower and higher chip levels. The vertical connection structures are placed so as to minimize a number of different spacing sizes between neighboring vertical connection structures across the vertical connection placement grid, while simultaneously minimizing to an extent possible layout area size. The vertical connection structures may be contacts or vias.

8448102, May 21, 2013

Jun 9, 2009

12/481445

Stephen Kornachuk - San Jose CA, US
Carole Lambert - San Jose CA, US
James Mali - La Selva Beach CA, US
Brian Reed - San Jose CA, US
Scott T. Becker - Scotts Valley CA, US

Tela Innovations, Inc. - Los Gatos CA

G06F 17/50
G06F 9/455

716 55, 716118, 716119, 716123, 716132

Within a dynamic array architecture, an irregular wire layout region within a portion of a chip level layout is bracketed by placing first and second regular wire layout shapes on a first and second sides, respectively, of the irregular wire layout region. One or more irregular wire layout shapes are placed within the irregular wire layout region. A first edge spacing is maintained between the first regular wire layout shape and a first outer irregular wire layout shape within the irregular wire layout region nearest to the first regular wire layout shape. A second edge spacing is maintained between the second regular wire layout shape and a second outer irregular wire layout shape within the irregular wire layout region nearest to the second regular wire layout shape. The first and second edge spacings are defined to optimize lithography of the regular and irregular wire layout shapes.

8453094, May 28, 2013

Jan 30, 2009

12/363705

Stephen Kornachuk - San Jose CA, US
Jim Mali - La Selva Beach CA, US
Carole Lambert - San Jose CA, US
Scott T. Becker - Scotts Valley CA, US

Tela Innovations, Inc. - Los Gatos CA

G06F 17/50

716126, 716118, 716119, 716122, 716123, 716124, 716125, 716132

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

2011015, Jun 30, 2011

Dec 29, 2010

12/981151

Stephen Kornachuk - San Jose CA, US

Tela Innovations, Inc. - Los Gatos CA

H01L 27/085
G06F 17/50

257392, 716104, 257E27059

A circuit is defined to operate in accordance with a common control signal. The circuit includes a plurality of transistors that have respective timing margins relative to the common control signal. Some of the plurality of transistors are defined differently from another of the plurality of transistors with regard to either transistor channel width, transistor channel length, transistor threshold voltage, or a combination thereof. The different definition of any given one of the plurality of transistors causes a reduction of either transistor power consumption, transistor current leakage, or a combination thereof, in exchange for a corresponding reduction in timing margin while maintaining a positive timing margin.

7577049, Aug 18, 2009

Aug 8, 2007

11/836099

Stephen Kornachuk - San Jose CA, US

Tela Innovations, Inc. - Campbell CA

G11C 7/00
G06F 12/00

365196, 365194, 3652101, 711167

A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense enable signal for the memory core, and a calibration side for determining when the sense enable signal is to be transmitted by the active side. Both the active side and the calibration side are defined to receive a timing signal. The active side is defined to transmit a delayed version of the timing signal as the sense enable signal for the memory core. The calibration side is defined to adjust the delay amount associated with the delayed version of the timing signal to be transmitted by the active side based on a determined sufficiency of the delay amount.