Stephen James Shannon, Age 3999 Bowers St, Jersey City, NJ 07307

2009024, Oct 1, 2009

Mar 28, 2008

12/057543

Sergio Schuler - Austin TX, US
Stephen R. Shannon - Austin TX, US
Michael D. Snyder - Austin TX, US

G06F 9/32

712238, 712E09075

A data processing system includes a branch target buffer (BTB) including a plurality of entries, each entry comprising a tag portion and a long branch indicator. The system also includes segment target address storage circuitry which stores a plurality of segment target addresses, index storage circuitry which stores a plurality of indices for indexing into the segment target address storage circuitry, and control circuitry which receives an instruction address and determines whether the instruction address matches a valid entry in the BTB. When the instruction address matches a valid entry in the BTB and the long branch indicator of the valid entry indicates a long branch, the index storage circuitry provides a selected index of the plurality of indices selected by the received instruction address. In response to the selected index, the segment target address storage circuitry provides a selected segment target address as a higher order target address portion.

2012011, May 10, 2012

Nov 8, 2010

12/941105

Suresh K. Venkumahanti - Austin TX, US
Lucian Codrescu - Austin TX, US
Stephen R. Shannon - Austin TX, US
Lin Wang - Austin TX, US
Phillip M. Jones - Austin TX, US
Daisy T. Palal - Las Vegas NV, US
Jiajin Tu - Austin TX, US

QUALCOMM INCORPORATED - San Diego CA

G06F 12/08

711125, 711E12016

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

2018008, Mar 22, 2018

Sep 22, 2016

15/273297

- San Diego CA, US
Aditi GORE - Austin TX, US
Stephen SHANNON - Austin TX, US
Matthew CUMMINGS - Round Rock TX, US

G06F 12/0864

Systems and methods for accessing a cache include determining if a current access of the cache will satisfy an expected relationship with a next access of the cache, wherein the cache is a set-associative cache comprising multiple ways. The next way for the next access is stored in a next way field associated with the current access. If the expected relationship will be satisfied, such as a sequential relationship which will be satisfied in the case of an instruction cache when the current access does not cause a change in control flow, the next way for the next access is retrieved from the next way field associated with the current access. The next way of the cache is then directly accessed using the retrieved next way.

2016032, Nov 10, 2016

Jul 15, 2016

15/211315

- San Diego CA, US
Stephen Robert Shannon - Austin TX, US

G06F 12/0855
G06F 12/0811

An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

2015034, Dec 3, 2015

May 27, 2014

14/287331

- San Diego CA, US
Stephen Robert Shannon - Austin TX, US

QUALCOMM Incorporated - San Diego CA

G06F 12/08

A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.

2015032, Nov 12, 2015

May 7, 2014

14/271812

- San Diego CA, US
Stephen Robert Shannon - Austin TX, US
Lin Wang - Austin TX, US

QUALCOMM Incorporated - San Diego CA

G06F 9/50
G06F 9/30

Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.