Stephen B Smetana, Age 71Minneapolis, MN

7146517, Dec 5, 2006

May 2, 2002

10/137060

Stephen B. Smetana - Eau Claire WI, US

Cray, Inc. - Seattle WA

G06F 1/04

713500, 713401

A clock for a computing system. The clock includes a first pulse shaver and a first pin connected to the first pulse shaver. The first pin selectively enables the first pulse shaver to reduce the width of enabling pulses in a clock signal passing through the first pulse shaver. A method for synchronizing data flow in a computing system. The method includes generating pulses; selectively reducing the width of the pulses; and delivering the pulses to a memory element.

5182473, Jan 26, 1993

Jan 22, 1992

7/826214

Jan A. Wikstrom - Chippewa Falls WI
Mark S. Birrittella - Chippewa Falls WI
David Kiefer - Chippewa Falls WI
Stephen B. Smetana - Eau Claire WI
Vernon W. Swanson - Chippewa Falls WI

Cray Research, Inc. - Chippewa Falls WI

H03K 1908

307454

Logic unit cells are disclosed, consisting of an array of high speed logic gates, the outputs of which are wired together and coupled to a low power driver. High speed and switching rates are achieved by using very fast logic gates which have no gain and make use of a wired logic function in order to effect two levels of logic without adding the propagation delay through another logic gate. These arrays of logic gates are coupled to drivers which restore logic levels and provide the necessary power for driving interconnect capacitances while consuming and dissipating a minimum of power in the process. Another logic circuit discloses an array of logic gates as inputs to another logic gate, the individual gates consisting of gallium arsenide components and having drivers built into the output stage of each gate.