Steven J Ratner, Age 812779 Glorietta Cir, Santa Clara, CA 95051

6678130, Jan 13, 2004

Mar 27, 2001

09/819293

Steven J. Ratner - Santa Clara CA
Hyoung Jo Youn - San Jose CA

Agilent Technologies, Inc. - Palo Alto CA

H02H 700

361 18, 361 56, 361 88, 361 911, 361 915, 361111, 361117, 361118

An electronic circuit consists of a voltage regulator and an electrostatic discharge (ESD) shunt. The voltage regulator maintains a prescribed voltage for the voltage supply of the chip. The ESD shunt protects the chip circuitry from undesirable levels of current or voltage. The voltage regulator and the ESD shunt share the functionality of a single, very large transistor. This combination results in a circuit with a smaller area, much smaller than if the two circuits had been built separately. With the reduction in area, both circuits can be manufactured on a single chip.

5506535, Apr 9, 1996

Jul 28, 1994

8/281897

Steven J. Ratner - Santa Clara CA

Hewlett-Packard Company - Palo Alto CA

H03K 190175

327333

An I/O circuit that provides bidirectional signal access to an integrated circuit (IC) core has voltage transformation capability to manage different voltage requirements. Although the I/O circuit and the core are fabricated from the same IC process, the I/O circuit can operate at non-process constrained voltages. The I/O circuit provides an output signal at the necessary voltage level to drive a component in the discrete environment while limiting the voltage supplied to the IC core to the maximum device voltage defined by the selected process.

5726587, Mar 10, 1998

Sep 3, 1996

8/711315

Steven J. Ratner - Santa Clara CA

Hewlett-Packard Company - Palo Alto CA

H03K 1901

326 56

An improved tri-state output buffer having an emitter-follower output stage clamps the reverse-bias voltage across the base-emitter path of an emitter-follower to limit the output leakage current and thereby extending the operating life of an integrated circuit (IC). A current sensitive voltage device such as a bipolar transistor or diode clamps the reverse-bias voltage of the base-emitter path. Voltage clamping prevents the bipolar transistors from activating while the buffer is disabled. The output leakage current that occurs when the junction is forward biased is minimized. This results in low output load capacitance that improves the propagation delay particularly when multiple buffers are used.