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Terry Sinclair Connacher, Age 641077 Carver Rd, Tempe, AZ 85284

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Known as:
Terry S Connacher
Related to:
Michael J Bentley George M Martinez 54

Terry Connacher Phones & Addresses

1077 Carver Rd, Tempe, AZ 85284 (480) 502-0058

Sedona, AZ

Chandler, AZ

8924 Palm Tree Dr, Scottsdale, AZ 85255 (480) 502-0058

Fountain Hills, AZ

Santa Ana, CA

Maricopa, AZ

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Terry Sinclair Connacher

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Work

Company: Motorola Jul 1995 to Nov 1999 Position: Hw design manager

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: University of the Pacific 1978 to 1983 Specialities: Electrical Engineering

Industries

Semiconductors

Mentions for Terry Sinclair Connacher

Terry Connacher resumes & CV records

Resumes

Terry Connacher Photo 10

Electrical Engineer Design Manager

Location:
Tempe, AZ
Industry:
Semiconductors
Work:
Motorola Jul 1995 - Nov 1999
Hw Design Manager Delta Design Jul 1995 - Nov 1999
Electrical Engineer Design Manager Mercury Defense Systems Mar 1989 - Jul 1995
Engineering Manager Hughes Aircraft Company Jun 1983 - Mar 1989
Member of Technical Staff
Education:
University of the Pacific 1978 - 1983
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering

Publications & IP owners

Us Patents

System For Testing A Group Of Ic-Chips Having A Chip Holding Subassembly That Is Built-In And Loaded/Unloaded Automatically

US Patent:
6919718, Jul 19, 2005
Filed:
Nov 10, 2003
Appl. No.:
10/705369
Inventors:
Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G01R001/04
G01R031/26
US Classification:
3241581, 324765
Abstract:
An electromechanical system for testing IC-chips includes a chip holding subassembly which has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the chip holding subassembly from a load position in the system to a test position in the system, and visa-versa; a temperature control mechanism which contacts the IC-modules on the chip holding subassembly only when that subassembly is at the test position; and a chip handler mechanism for automatically moving the IC-modules into and out of the sockets, when the chip holding subassembly is at the load position. At the test position, the temperature control mechanism contacts the IC-modules to control their temperature. At the load position, the chip handler mechanism automatically unloads one group of IC-modules from the sockets on the chip holding subassembly and automatically loads another group of the IC-modules into the sockets.

System For Testing One Or More Groups Of Ic-Chips While Concurrently Loading/Unloading Another Group

US Patent:
6924636, Aug 2, 2005
Filed:
Nov 10, 2003
Appl. No.:
10/705524
Inventors:
Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G01R001/04
G01R031/26
US Classification:
3241581, 324765
Abstract:
An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies, where N is an integer greater than one and where each chip holding subassembly has sockets for holding a group of IC-modules that include the IC-chips; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to a test position in the system, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a temperature control mechanism which contacts the IC-modules at the test position. Between the moving of the i-th chip holding subassembly and the next chip holding subassembly in the sequence, the IC-chips are burn-in tested on all N of the chip holding subassemblies. Also, while the i-th chip holding subassembly is being moved, burn-in testing of IC-chips on the remaining N-1 chip holding subassemblies continues.

Electromechanical Module, For Holding Ic-Chips In A Chip Testing System, That Synchronizes And Translates Test Signals To The Ic-Chips

US Patent:
6958617, Oct 25, 2005
Filed:
Jan 16, 2004
Appl. No.:
10/759910
Inventors:
James Vernon Rhodes - Chandler AZ, US
Robert Howard Carlson - Aliso Viejo CA, US
Terry Sinclair Connacher - Scottsdale AZ, US
Carl Larry Ostrowski - Pinckney MI, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G01R031/02
US Classification:
324754, 3241581
Abstract:
An electromechanical module, for holding IC-chips in a chip testing system, includes a circuit board having a plurality of sockets mounted thereon. Each socket is structured to hold one IC-chip that is to be tested, and each socket has a corresponding register on the circuit board. In addition, a bus is on the circuit board, which—a) sends a timing pulse to a clock input on all of the registers in parallel, and b) concurrently sends a clock signal and N−1 test signals to N data inputs on all of the registers. Further, each socket has N input terminals that are connected to N outputs on a respective set of signal translators on the circuit board, and each set of signal translators has N inputs that are connected to N data outputs on the socket's corresponding register.

System For Testing Multiple Groups Of Ic-Chips Which Concurrently Sends Time-Shifted Test Signals To The Groups

US Patent:
6909299, Jun 21, 2005
Filed:
Nov 10, 2003
Appl. No.:
10/705368
Inventors:
Randy Neaman Siade - Chandler AZ, US
Terry Sinclair Connacher - Scottsdale AZ, US
James Vernon Rhodes - Chandler AZ, US
James Mason Brafford - Mission Viejo CA, US
John Charles Montgomery - Poway CA, US
David Jon Mortensen - Mission Viejo CA, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G01R031/02
US Classification:
324755, 324760
Abstract:
An electromechanical system for testing IC-chips includes a total of N chip holding subassemblies; a moving mechanism for automatically moving the i-th chip holding subassembly from a load position in the system to the test position in the systems, and visa-versa, where i ranges from 1 to N and changes with time in a sequence; and a signal generator which sends test signals to the IC-chips at the test position. Between the moving of the i-th chip holding subassembly and the next subassembly in the sequence, test signals are sent to the IC-chips on all N of the chip holding subassemblies such that the signals are shifted in time from one subassembly to another. Also, while the i-th chip holding subassembly is being moved, the time shifted test signals continue to be sent to the IC-chips on the remaining N−1 chip holding subassemblies.

Possible Relatives

David L Connacher  Terry M Standley  Terry L Stanfield  Terry G Stanford  Terry L White  Terry L Jolly  Terry E Jones  Terry E Stanger  Terry W Stansbury  Terry L Stanton 

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