Terry L Lyon, Age 751430 Silk Oak Dr, Fort Collins, CO 80525

6427188, Jul 30, 2002

Feb 9, 2000

09/501396

Terry L Lyon - Fort Collins CO
Eric R DeLano - Ft Collins CO
Dean A. Mulla - Saratoga CA

Hewlett-Packard Company - Palo Alto CA

G06F 1200

711122

A system and method are disclosed which determine in parallel for multiple levels of a multi-level cache whether any one of such multiple levels is capable of satisfying a memory access request. Tags for multiple levels of a multi-level cache are accessed in parallel to determine whether the address for a memory access request is contained within any of the multiple levels. For instance, in a preferred embodiment, the tags for the first level of cache and the tags for the second level of cache are accessed in parallel. Also, additional levels of cache tags up to N levels may be accessed in parallel with the first-level cache tags. Thus, by the end of the access of the first-level cache tags it is known whether a memory access request can be satisfied by the first-level, second-level, or any additional N-levels of cache that are accessed in parallel. Additionally, in a preferred embodiment, the multi-level cache is arranged such that the data array of a level of cache is accessed only if it is determined that such level of cache is capable of satisfying a received memory access request. Additionally, in a preferred embodiment the multi-level cache is partitioned into N ways of associativity, and only a single way of a data array is accessed to satisfy a memory access request, thereby preserving the remaining ways of a data array to save power and resources that may be accessed to satisfy other instructions.

6470437, Oct 22, 2002

Dec 17, 1999

09/466306

Terry L Lyon - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1210

711207, 711144

In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits may include a translation lookaside buffer (TLB) architecture to handle store operations in parallel with a smaller, faster integer load TLB architecture. A store valid module is added to the TLB architecture. The store valid module sets a valid bit when a new cache line is written. The valid bit is cleared on the occurrence of an invalidation operation. The valid bit prevents multiple store updates or invalidates for cache lines that are already invalid. In addition, an invalidation will block load hits on the cache line. A control logic is added to remove stale cache lines.

6493792, Dec 10, 2002

Jan 31, 2000

09/495155

Stephen R. Undy - Ft. Collins CO
Terry L Lyon - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G11C 1500

711108, 711128, 365 49

A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a âhitâ signal if the selected bit is the same as the corresponding bit of the stored tag value. Storage means are employed for recording the results of the compare with the M hit signal.

6493812, Dec 10, 2002

Dec 17, 1999

09/465722

Terry L Lyon - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06F 1210

711207, 711108, 711210, 711128

A computer micro-architecture employing a prevalidated cache tag design includes circuitry to support virtual address aliasing and multiple page sizes. Support for various levels of address aliasing are provided through a physical address CAM, page size mask compares and a column copy tag function. Also supported are address aliasing that invalidates aliased lines, address aliasing with TLB entries with the same page sizes, and address aliasing the TLB entries of different sizes. Multiple page sizes are supported with extensions to the prevalidated cache tag design by adding page size mask RAMs and virtual and physical address RAMs.

6507892, Jan 14, 2003

Feb 21, 2000

09/510285

Dean A. Mulla - Saratoga CA
Terry L Lyon - Fort Collins CO
Reid James Riedlinger - Fort Collins CO
Tom Grutkowski - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA
Intel Corporation - Santa Clara CA

G06F 1300

711131, 711117, 711119, 711149

The inventive cache processes multiple access requests simultaneously by using separate queuing structures for data and instructions. The inventive cache uses ordering mechanisms that guarantee program order when there are address conflicts and architectural ordering requirements. The queuing structures are snoopable by other processors of a multiprocessor system. The inventive cache has a tag access bypass around the queuing structures, to allow for speculative checking by other levels of cache and for lower latency if the queues are empty. The inventive cache allows for at least four accesses to be processed simultaneously. The results of the access can be sent to multiple consumers. The multiported nature of the inventive cache allows for a very high bandwidth to be processed through this cache with a low latency.

6557078, Apr 29, 2003

Feb 21, 2000

09/510283

Dean A. Mulla - Saratoga CA
Terry L Lyon - Fort Collins CO
Reid James Riedlinger - Fort Collins CO
Thomas Grutkowski - Fort Collins CO

Hewlett Packard Development Company, L.P. - Houston TX
Intel Corporation - Santa Clara CA

G06F 1300

711122, 711131, 711120, 711119

The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

6591393, Jul 8, 2003

Feb 18, 2000

09/507208

Shawn Kenneth Walker - Fort Collins CO
Dean A. Mulla - Saratoga CA
Terry L Lyon - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G11C 2900

714763

Methods and apparatus mask the latency of error detection and/or error correction applied to data transferred between a first memory and a second memory. The method comprises determining whether there is an error in a data unit in the first memory; transferring data based on the data unit from the first memory to a second memory, wherein the transferring step commences before completion of the determining step; and disabling at least part of the second memory if the determining step detects an error in the data unit. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory.

6625714, Sep 23, 2003

Dec 17, 1999

09/466494

Terry L Lyon - Fort Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1210

711207, 711168

In a computer system, a parallel, distributed function lookaside buffer (TLB) includes a small, fast TLB and a second larger, but slower TLB. The two TLBs operate in parallel, with the small TLB receiving integer load data and the large TLB receiving other virtual address information. By distributing functions, such as load and store instructions, and integer and floating point instructions, between the two TLBs, the small TLB can operate with a low latency and avoid thrashing and similar problems while the larger TLB provides high bandwidth for memory intensive operations. This mechanism also provides a parallel store update and invalidation mechanism which is particularly useful for prevalidated cache tag designs.