Thomas K Chadwick, Age 75PO Box 648, Richfield Springs, NY 13439

6341079, Jan 22, 2002

May 23, 2001

09/863848

Thomas B. Chadwick - Essex Junction VT

International Business Machines Corporation - Armonk NY

G11C 1500

365 49, 36518907, 711108

A content addressable memory device comprises a NAND-NOR chain comprised an alternating sequence of NAND and NOR stages; the NAND stages, each including a first CAM cell comprising a first memory cell that stores a first data bit and a first compare cell that compares the first data bit with a first compare bit and generates a first compare signal indicating whether the first data bit matches the first compare bit and a logical NAND gate that combines the first compare signals of other first CAM cells in the NAND stage; the NOR stages, each including a second CAM cell comprising a second memory cell that stores a second data bit and a second compare cell that compares the second data bit with a second compare bit and generates a second compare signal indicating whether the second data bit matches the second compare bit and a logical NOR gate that combines the second compare signals of other second CAM cells in the NOR stage; and the NAND-NOR chain generating a match signal indicating a match of all the compare bits to all the data bits in the content addressable memory device.

6430072, Aug 6, 2002

Oct 1, 2001

09/682638

Thomas B. Chadwick - Essex Junction VT
Rahul K. Nadkarni - Colchester VT
Michael R. Ouellette - Westford VT
Jeremy P. Rowland - South Burlington VT

International Business Machines Corporation - Armonk NY

G11C 1500

365 49, 36518907, 365201

A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.

6552920, Apr 22, 2003

Jun 27, 2001

09/892396

Thomas B. Chadwick - Essex Junction VT
Tarl S. Gordon - South Burlington VT
Eric Jasinski - Colchester VT
Rahul Nadkarni - Colchester VT
Michael R. Ouellette - Westford VT

International Business Machines Corporation - Armonk NY

G11C 1500

365 49, 36518907, 365203

A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

6711040, Mar 23, 2004

Jan 28, 2003

10/353119

Thomas B. Chadwick - Essex Junction VT
Tari S. Gordon - Burlington VT
Eric Jasinski - Colchester VT
Rahul Nadkarni - Colchester VT
Michael R. Quellette - Westford VT

International Business Machines Corporation - Armonk NY

G11C 1500

365 49, 365201, 36518907

A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

6920525, Jul 19, 2005

Jul 19, 2002

10/199788

Thomas B. Chadwick - Essex Junction VT, US
Tarl S. Gordon - Leander TX, US
Rahul K. Nadkarni - Colchester VT, US
Michael R. Ouellette - Westford VT, US
Jeremy Rowland - South Burlington VT, US

International Business Machines Corporation - Armonk NY

G06F012/00

711108, 714711, 714718, 365 49, 365 52, 365200, 36523006

A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.

2007022, Sep 27, 2007

Mar 24, 2006

11/277385

Thomas Chadwick - Essex Junction VT, US
Margaret Charlebois - Jericho VT, US
David Hathaway - Underhill VT, US
Jason Rotella - Mineville NY, US
Douglas Stout - Milton VT, US
Ivan Wemple - Shelburne VT, US

G06F 17/50
G06F 9/45

716006000

A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

2008027, Oct 30, 2008

Jun 13, 2008

12/138871

Thomas B. Chadwick - Essex Junction VT, US
Margaret R. Charlebois - Jericho VT, US
David J. Hathaway - Underhill VT, US
Jason E. Rotella - Mineville NY, US
Douglas W. Stout - Milton VT, US

G06F 17/50

716 6

A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

2016022, Aug 4, 2016

Feb 1, 2016

15/012707

- Santa Clara CA, US
Thomas Chadwick - Essex VT, US
Nancy Pratt - Essex VT, US

G06F 11/27

A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.