Thomas M Deneau, Age 74604 Rainbow Cv, West Lake Hills, TX 78746

8156286, Apr 10, 2012

Dec 30, 2008

12/346154

Thomas M. Deneau - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 12/08

711137, 711E12004, 712 E9047

A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon previous memory accesses. The prefetch unit may be further configured to use addresses of the memory accesses that miss to calculate each next memory block to prefetch. The detection logic may be configured to provide a notification to the prefetch unit in response to detecting a memory access instruction including a particular hint. In response to receiving the notification, the prefetch unit may be configured to inhibit using an address associated with the memory access instruction including the particular hint, when calculating subsequent memory blocks to prefetch.

2011007, Mar 31, 2011

Sep 25, 2009

12/567267

Thomas M. Deneau - Austin TX, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G06F 9/44
G06F 7/42

717106, 708680

Disclosed are methods, apparatus, and computer-readable media for generating output computer code that adds a 64-bit integer to a smaller-length integer having a length of less than 64 bits. Input computer code includes a loop that includes adding a 64-bit integer and a smaller-length integer. Output code is generated that represents the input code in a format such as assembly language or machine code. The output code includes instructions to convert the smaller-length integer to a 64-bit integer, such that the conversion is not performed during each loop execution. The smaller-length integer is converted by subtracting an offset from the 64-bit integer, adding the offset to the smaller-length integer, and zero-extending the smaller-length integer. The offset is determined based on the length of the smaller-length integer. The output code preserves the integer semantics of the smaller-length integer as required by the input code.

2011014, Jun 16, 2011

Dec 14, 2009

12/637022

Shrinivas B. Joshi - Austin TX, US
Thomas M. Deneau - Austin TX, US

G06F 12/08
G06F 12/00
G06F 9/45

711125, 711137, 717148, 711E12001, 711E12057, 711E1202

A technique for prefetching data into a cache memory system includes prefetching data based on meta information indicative of data access patterns. A method includes tagging data of a program with meta information indicative of data access patterns. The method includes prefetching the data from main memory at least partially based on the meta information, by a processor executing the program. In at least one embodiment, the method includes generating an executable at least partially based on the meta information. The executable includes at least one instruction to prefetch the data. In at least one embodiment, the method includes inserting one or more instructions for prefetching the data into an intermediate form of program code while translating program source code into the intermediate form of program code.

6684305, Jan 27, 2004

Apr 24, 2001

09/841469

Thomas M. Deneau - Austin TX

Advanced Micro Devices, Inc. - Austin TX

G06F 1210

711159, 711133, 711141, 711155, 711160, 711156

A computer system including a first processor, a second processor in communication with the first processor, a memory coupled to the first and second processors (i. e. , a shared memory) and including multiple memory locations, and a storage device coupled to the first processor. The first and second processors implement virtual memory using the memory. The first processor maintains a first set of page tables and a second set of page tables in the memory. The first processor uses the first set of page tables to access the memory locations within the memory. The second processor uses the second set of page tables, maintained by the first processor, to access the memory locations within the memory. A virtual memory page replacement method is described for use in the computer system, wherein the virtual memory page replacement method is designed to help maintain paged memory coherence within the multiprocessor computer system.