Thomas Walter Liston, Age 581629 Maize Bend Dr, Austin, TX 78727

6590818, Jul 8, 2003

Jun 17, 2002

10/173229

Thomas W. Liston - Austin TX
Lawrence N. Herr - Coupland TX

Motorola, Inc. - Schaumburg IL

G11C 700

365201, 365200, 365202, 365203, 365188

A method and apparatus for soft defect detection in a memory is disclosed. Bit lines are conditioned to predetermined voltages which ensure that, upon activation of the corresponding word line, all the storage transistors within the corresponding bit cells (at the intersection of the bit lines and the word line) are electrically conductive. A change in state of the bit cell in response to activation of the corresponding word line indicates the presence of a soft defect. An evaluator coupled to the memory may be used to identify defective memories by comparing the results of the testing to determine if any bit cells changed states. In one embodiment, the conditioning of the bit lines includes charging a bit line to a first predetermined voltage and its corresponding complementary bit line to a second predetermined voltage and then connecting the bit line and complementary bit line together to equalize the voltages.

7440354, Oct 21, 2008

May 15, 2006

11/433998

Thomas W. Liston - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/00

365227, 365228, 36523006, 36518911

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

7554841, Jun 30, 2009

Sep 25, 2006

11/534715

Thomas W. Liston - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 11/00

36518501, 365154, 365227

A circuit has a storing portion, a write portion and a read portion. In one embodiment, read portion has a transistor which has a substantially thinner gate oxide than the transistors in the storing portion and the transistors in the write portion. In an alternate embodiment, circuit has a plurality of read ports. In an alternate embodiment, selecting the optimal gate oxide thickness for the transistors in circuit allows the trade-off between transistor switching speed and gate leakage current to be optimized to produce a circuit having a fast enough read access time and a low enough standby power.

7706207, Apr 27, 2010

Sep 12, 2008

12/209477

Thomas W. Liston - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 8/00

36523003, 36518911, 365 63

A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

7940599, May 10, 2011

Mar 16, 2009

12/404892

Olga R. Lu - Austin TX, US
Lawrence F. Childs - Austin TX, US
Thomas W. Liston - Austin TX, US

Freescale Semiconductor, Inc. - Austin TX

G11C 7/00
G11C 7/10
G11C 8/00

36523005, 36518904, 365202, 365203

A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.

2013029, Oct 31, 2013

Apr 26, 2012

13/457248

Jianan Yang - Austin TX, US
Mark W. Jetton - Austin TX, US
Thomas W. Liston - Austin TX, US

FREESCALE SEMICONDUCTOR, INC. - Austin TX

G06F 1/32
G06F 1/00

713320, 713300

In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

2013029, Oct 31, 2013

Nov 29, 2012

13/689331

Jianan Yang - Austin TX, US
Mark W. Jetton - Austin TX, US
Thomas W. Liston - Austin TX, US
George P. Hoekstra - Austin TX, US
Andrew C. Russell - Austin TX, US

G06F 1/26
G06F 1/32

713320, 713300

In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

2013034, Dec 26, 2013

Jun 26, 2012

13/532804

Ashish Sharma - New Delhi, IN
James B. Eifert - Austin TX, US
Amit Kumar Gupta - Greater Noida, IN
Thomas W. Liston - Austin TX, US
Jehoda Refaeli - Austin TX, US

FREESCALE SEMICONDUCTOR, INC - Austin TX

G11C 7/10

36518905

A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.