Li Ching Tsai, Age 707945 Livingston Ln, Fort Collins, CO 80525

6594772, Jul 15, 2003

Jan 14, 2000

09/483283

Li C Tsai - Ft Collins CO
Daniel Krueger - Ft Collins CO
Johnny Q Zhang - San Jose CA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 104

713500, 713400, 713401, 713501, 713502, 713503

Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit. A measure of clock wave skew of the integrated circuit chip is obtained by connecting a clock coupling circuit and a separate node in a path extending between the most distant nodes on the chip. The path includes a phase detector responsive to clock waves supplied to the distantly spaced node and the node of the path extending between the most distant nodes on the chip.

6665698, Dec 16, 2003

May 12, 2000

09/569658

Li C Tsai - Ft Collins CO
Daniel Krueger - Ft Collins CO

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 750

708672

A high speed incrementer/decrementer design is presented that computes the propagate, generate, and kill signals which are used to compute carries and sums from the incrementer inputs. By setting one input to â0â and the carry-in to â1â, the adder is used as an incrementer. In the design of the invention, a bit-wise decision is made whether to complement the input bit or not. The design also allows decrementing and supports both unsigned and 2s complement number representations.

7120815, Oct 10, 2006

Oct 31, 2003

10/697297

Li Tsai - Fort Collins CO, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1/12
G06F 13/42

713400, 713401

Clock circuitry supplies synchronized clock waves to loads on plural integrated circuit chips. The clock circuitry couples the synchronized clock waves to regions of the chips. There is a first clock wave route in a first direction from a first chip to a second chip and a second clock wave route in a second direction from the second chip to the first chip. The routes have substantially the same geometry and are in close proximity to each other so they have substantially the same effects on clock waves propagating therein in opposite directions. A phase detector and lowpass filter on the first chip responds to (1) a clock wave source and (2) a clock wave derived on a chip other than the first chip, to supply, via a common mode line, a control for voltage controlled delays of the chips other than the third chip.

6041092, Mar 21, 2000

Oct 30, 1998

9/183311

Li C. Tsai - Fort Collins CO
Richard M. Blumberg - Fort Collins CO

Hewlett-Packard Company - Palo Alto CA

G06M 300

377 1

A digital circuit for counting the number of zeroes or ones in a data word comprising a plurality of series paths leading to one-hot encoded outputs. Each one-hot encoded output indicates a different number of like signals in the input data word. One of the plurality of series paths is activated by connecting the series path from an input power rail to the one-hot output. A series path is connected through a plurality of transfer gates, each controlled by either a single bit of the input data word or its complement. The series paths may be optimized to share transfer gates by interconnecting them in a tree or lattice structure. Subsections of the input data word may be counted separately in independent tree or lattice structures, then combined in subsequent combinational stages of the circuit. The resulting one-hot encoded count of like signals may then be binary encoded by a final stage of the counting circuit.