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Tyler Thorp81 Oakes Blvd, San Leandro, CA 94577

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Tyler Thorp Phones & Addresses

81 Oakes Blvd, San Leandro, CA 94577

Work

Company: Vierra Magen Marcus LLP Address: 575 Market St Ste 3750, San Francisco, CA 94105 Specialities: Antitrust / Trade Law - 34% • Appeals - 33% • Construction / Development - 33%

Education

School / High School: Santa Clara Univ SOL

Ranks

Licence: California - Active Date: 2011

Mentions for Tyler Thorp

Career records & work history

Lawyers & Attorneys

Tyler Thorp Photo 1

Tyler J Thorp, San Francisco CA - Lawyer

Address:
Vierra Magen Marcus LLP
575 Market St Ste 3750, San Francisco, CA 94105
(415) 489-4100 (Office)
Licenses:
California - Active 2011
Education:
Santa Clara Univ SOL
University of Washington
Specialties:
Antitrust / Trade Law - 34%
Appeals - 33%
Construction / Development - 33%
Tyler Thorp Photo 2

Tyler Thorp - Lawyer

Office:
Seed IP Law Group LLP
Specialties:
Antitrust / Trade Law, Appeals, Construction / Development, Construction / Development
ISLN:
921711313
Admitted:
(Admission pending)
Law School:
Santa Clara University School of Law Santa Clara CA, J.D.

Tyler Thorp resumes & CV records

Resumes

Tyler Thorp Photo 17

Tyler Thorp

Location:
San Francisco Bay Area
Industry:
Semiconductors
Tyler Thorp Photo 18

Tyler Thorp

Publications & IP owners

Us Patents

Cmos-Microprocessor Chip And Package Anti-Resonance Method

US Patent:
6456107, Sep 24, 2002
Filed:
Jan 4, 2001
Appl. No.:
09/754573
Inventors:
Claude R. Gauthier - Fremont CA
Tyler J. Thorp - Sunnyvale CA
Richard L. Wheeler - San Jose CA
Brian Amick - Plano TX
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H03K 19003
US Classification:
326 27, 326 30, 326 83
Abstract:
A method for regulating resonance in a micro-chip has been developed. The circuit includes an on-chip de-coupled capacitor that is shunted across the supply and ground voltages, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

Integrated Circuit Performance And Reliability Using Angle Measurement For A Patterned Bump Layout On A Power Grid

US Patent:
6473883, Oct 29, 2002
Filed:
Nov 29, 2001
Appl. No.:
09/997437
Inventors:
Sudhakar Bobba - Sunyvale CA
Tyler Thorp - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1750
US Classification:
716 2, 356608, 716 10, 716 11, 716 12, 716 13
Abstract:
A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

Method For Reducing Supply Noise Near An On-Die Thermal Sensor

US Patent:
6476663, Nov 5, 2002
Filed:
Aug 14, 2001
Appl. No.:
09/929151
Inventors:
Claude R. Gauthier - Fremont CA
Brian W. Amick - Austin TX
Tyler J. Thorp - Sunnyvale CA
Dean Liu - Sunnyvale CA
Pradeep R. Trivedi - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H01L 3500
US Classification:
327513, 327552
Abstract:
A method for reducing power supply noise in the power supply system of a thermal sensor has been developed. The method includes powering up a thermal sensor and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the thermal sensor.

Cmos-Microprocessor Chip And Package Anti-Resonance Apparatus

US Patent:
6483341, Nov 19, 2002
Filed:
Jan 4, 2001
Appl. No.:
09/754564
Inventors:
Claude R. Gauthier - Fremont CA
Tyler J. Thorp - Sunnyvale CA
Richard L. Wheeler - San Jose CA
Brian Amick - Plano TX
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 1716
US Classification:
326 30, 326 83, 326 26
Abstract:
An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.

60 Degree Bump Placement Layout For An Integrated Circuit Power Grid

US Patent:
6495926, Dec 17, 2002
Filed:
Nov 29, 2001
Appl. No.:
09/997471
Inventors:
Sudhakar Bobba - Sunnyvale CA
Tyler Thorp - Sunnyvale CA
Dean Liu - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - CA
International Classification:
H01L 2348
US Classification:
257786, 257780
Abstract:
A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Method For Reducing Peak To Peak Jitter In A Dual-Loop Delay Locked Loop

US Patent:
6501328, Dec 31, 2002
Filed:
Aug 14, 2001
Appl. No.:
09/930435
Inventors:
Claude R. Gauthier - Fremont CA
Brian W. Amick - Austin TX
Tyler J. Thorp - Sunnyvale CA
Dean Liu - Sunnyvale CA
Pradeep R. Trivedi - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - CA
International Classification:
H03B 100
US Classification:
327551
Abstract:
A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.

Current Crowding Reduction Technique For Flip Chip Package Technology

US Patent:
6566758, May 20, 2003
Filed:
Nov 27, 2001
Appl. No.:
09/995168
Inventors:
Pradeep Trivedi - Sunnyvale CA
Tyler Thorp - Sunnyvale CA
Sudhakar Bobba - Sunnyvale CA
Dean Liu - Sunyvale CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
H01L 2348
US Classification:
257774, 257778, 257786, 438629, 438666
Abstract:
A current crowding reduction technique involving the uniform displacement of vias around a bump is provided. By uniformly arranging vias around the bump on an integrated circuit, current can uniformly flow to and from the bump, effectively leading to reduced current density around the bump. Further, a method for reducing current crowding around a bump using an uniform arrangement of vias around the bump is provided.

Method For Smoothing Di/Dt Noise Due To Clock Transitions

US Patent:
6515527, Feb 4, 2003
Filed:
Jun 22, 2001
Appl. No.:
09/887395
Inventors:
Tyler J. Thorp - Sunnyvale CA
Brian W. Amick - Sunnyvale CA
Dean liu - Sunnyvale CA
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H03K 512
US Classification:
327170, 327165, 327299
Abstract:
A method for increasing a transition time period for an edge transition of a clock signal has been developed. The method includes detecting an edge transition of a clock signal of a computer system. Next, additional system power consumption is initiated upon detection of the edge transition. This additional power consumption will lengthen the edge transition time period of the clock signal.

Possible Relatives

Dale Thorp  Deborah L Thorp  Daniel L Thorp  Douglas R Thorp  Edward A Thorp  Erin P Thorp  Gary D Thorp  Tyler J White  Tyler P Stanton  Tyler J Staples 

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