Vinod Grover resumes & CV records
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Vinod Kumar Grover Deceased36918 Bolina Ter, Fremont, CA 94536
Vinod Grover Phones & Addresses
36918 Bolina Ter, Fremont, CA 94536 (510) 796-1715
4950 Stevenson Blvd #105, Fremont, CA 94538
39655 Trinity Way #8108, Fremont, CA 94538
Kennedale, TX
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Publications & IP owners
Us Patents
Software Filtering In A Transactional Memory System
US Patent:
2010021, Aug 26, 2010
Filed:
Dec 15, 2009
Appl. No.:
12/653471
Inventors:
Ali-Reza Adl-Tabatabai - San Jose CA, US
David Callahan - Seattle WA, US
Jan Gray - Bellevue WA, US
Vinod Grover - Mercer Island WA, US
Bratin Saha - Santa Clara CA, US
Gad Sheaffer - Haifa, IL
David Callahan - Seattle WA, US
Jan Gray - Bellevue WA, US
Vinod Grover - Mercer Island WA, US
Bratin Saha - Santa Clara CA, US
Gad Sheaffer - Haifa, IL
International Classification:
G06F 9/46
US Classification:
718107
Abstract:
A method and apparatus for utilizing hardware mechanisms of a transactional memory system is herein described. Various embodiments relate to software-based filtering of operations from read and write barriers and read isolation barriers during transactional execution. Other embodiments relate to software-implemented read barrier processing to accelerate strong atomicity. Other embodiments are also described and claimed.
Method For Transforming A Multithreaded Program For General Execution
US Patent:
2012025, Oct 4, 2012
Filed:
Mar 30, 2011
Appl. No.:
13/076258
Inventors:
Jaydeep MARATHE - Santa Clara CA, US
Vinod Grover - Mercer Island WA, US
Vinod Grover - Mercer Island WA, US
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
A technique is disclosed for executing a program designed for multi-threaded operation on a general purpose processor. Original source code for the program is transformed from a multi-threaded structure into a computationally equivalent single-threaded structure. A transform operation modifies the original source code to insert code constructs for serial thread execution. The transform operation also replaces synchronization barrier constructs in the original source code with synchronization barrier code that is configured to facilitate serialization. The transformed source code may then be conventionally compiled and advantageously executed on the general purpose processor.
Technique For Inter-Procedural Memory Address Space Optimization In Gpu Computing Compiler
US Patent:
2013011, May 9, 2013
Filed:
Oct 24, 2012
Appl. No.:
13/659802
Inventors:
NVIDIA CORPORATION - Santa Clara CA, US
Jian-Zhong WANG - Fremont CA, US
Yuan LIN - Cupertino CA, US
Vinod GROVER - Mercer Island WA, US
Jian-Zhong WANG - Fremont CA, US
Yuan LIN - Cupertino CA, US
Vinod GROVER - Mercer Island WA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 15/80
US Classification:
345505
Abstract:
A device compiler and linker is configured to optimize program code of a co-processor enabled application by resolving generic memory access operations within that program code to target specific memory spaces. In situations where a generic memory access operation cannot be resolved and may target constant memory, constant variables associated with those generic memory access operations are transferred to reside in global memory.
Technique For Live Analysis-Based Rematerialization To Reduce Register Pressures And Enhance Parallelism
US Patent:
2013011, May 9, 2013
Filed:
Nov 5, 2012
Appl. No.:
13/669401
Inventors:
NVIDIA Corporation - Santa Clara CA, US
Jian-Zhong WANG - Fremont CA, US
Yuan LIN - Cupertino CA, US
Vinod GROVER - Mercer Island WA, US
Jian-Zhong WANG - Fremont CA, US
Yuan LIN - Cupertino CA, US
Vinod GROVER - Mercer Island WA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717149
Abstract:
A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.
Algorithm For 64-Bit Address Mode Optimization
US Patent:
2013011, May 9, 2013
Filed:
Oct 24, 2012
Appl. No.:
13/659786
Inventors:
NVIDIA Corporation - Santa Clara CA, US
JIAN-ZHONG WANG - Fremont CA, US
VINOD GROVER - Mercer Island WA, US
JIAN-ZHONG WANG - Fremont CA, US
VINOD GROVER - Mercer Island WA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717151
Abstract:
One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.
Method And System For Run Time Detection Of Shared Memory Data Access Hazards
US Patent:
2013030, Nov 14, 2013
Filed:
Dec 27, 2012
Appl. No.:
13/728990
Inventors:
Jaydeep Marathe - San Jose CA, US
Manjunath Kudlur - San Jose CA, US
Vinod Grover - Mercer Island WA, US
Geoffrey Gerfin - Sunnyvale CA, US
Alban Douillet - Cupertino CA, US
Mayank Kaushik - Santa Clara CA, US
Manjunath Kudlur - San Jose CA, US
Vinod Grover - Mercer Island WA, US
Geoffrey Gerfin - Sunnyvale CA, US
Alban Douillet - Cupertino CA, US
Mayank Kaushik - Santa Clara CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
G06F 3/06
US Classification:
711150
Abstract:
A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.
Method And System For Heterogeneous Filtering Framework For Shared Memory Data Access Hazard Reports
US Patent:
2013030, Nov 14, 2013
Filed:
Dec 27, 2012
Appl. No.:
13/728968
Inventors:
Manjunath Kudlur - San Jose CA, US
Vinod Grover - Mercer Island WA, US
Vinod Grover - Mercer Island WA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G06F 3/06
US Classification:
718103, 718102
Abstract:
A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.
Method, Apparatus, System And Computer Program Product For Initializing A Data Structure At Its First Active Use
US Patent:
6148302, Nov 14, 2000
Filed:
Feb 26, 1998
Appl. No.:
9/031229
Inventors:
Boris Beylin - Palo Alto CA
Vinod Grover - Piedmont CA
Vinod Grover - Piedmont CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 700
G06F 1200
G06F 1200
US Classification:
707102
Abstract:
Apparatus, methods, systems and computer program products are disclosed that provide an efficient mechanism for invoking a programmed operation at the first active use of the OOP object or data structure. The programmed operation can be used to initialize an object-oriented programming (OOP) object or data structure. The first active use of the data structure or OOP object is detected because the initial access mechanism is constrained to cause a misaligned memory access fault (trap) by attempting a non-byte access-mode memory access to an odd byte address. As the fault is processed, the access mechanism is converted so that the initial and subsequent non-byte access-mode memory accesses will succeed. In addition, the OOP object or data structure is initialized. Then the initial access attempt is repeated on the just initialized OOP object or data structure using the converted access mechanism.
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