Wen Tu, Age 4513654 South Springs Dr, Clifton, VA 20124

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13654 South Springs Dr, Clifton, VA 20124 (703) 815-0452

San Jose, CA

San Francisco, CA

Centreville, VA

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Wen Tu

Location:
United States

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Us Patents

Method And Apparatus For Forming Metal Interconnects

US Patent:
6372633, Apr 16, 2002
Filed:
Jul 8, 1998
Appl. No.:
09/111657
Inventors:
Dan Maydan - Los Altos Hills CA
Ashok K. Sinha - Palo Alto CA
Zheng Xu - Foster City CA
Liang-Yu Chen - Foster City CA
Roderick Craig Mosely - Pleasanton CA
Daniel Carl - Pleasanton CA
Diana Xiaobing Ma - Saratoga CA
Yan Ye - Campbell CA
Wen Chiang Tu - Sunnyvale CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 214763
US Classification:
438637, 257763
Abstract:
The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

Method And Apparatus For Forming Metal Interconnects

US Patent:
2002005, May 16, 2002
Filed:
Jan 10, 2002
Appl. No.:
10/043422
Inventors:
Dan Maydan - Los Altos CA, US
Ashok Sinha - Palo Alto CA, US
Zheng Xu - Foster City CA, US
Liang-Yuh Chen - Foster City CA, US
Roderick Mosely - Pleasanton CA, US
Daniel Carl - Pleasanton CA, US
Diana Ma - Saratoga CA, US
Yan Ye - Campbell CA, US
Wen Tu - Sunnyvale CA, US
Assignee:
Applied Materials, Inc.
International Classification:
H01L021/4763
US Classification:
438/637000
Abstract:
The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

Robot Blade For Handling Of Semiconductor Substrate

US Patent:
6024393, Feb 15, 2000
Filed:
Nov 4, 1996
Appl. No.:
8/740886
Inventors:
Behzad Shamlou - San Jose CA
Wen Chiang Tu - Mountain View CA
Xuyen Pham - Fremont CA
Yu Chang - San Jose CA
Daniel O. Clark - Pleasanton CA
Shun Wu - Cupertino CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
B25J 1506
B65G 4907
US Classification:
294 641
Abstract:
The amount of particulate contamination produced due to rubbing between a semiconductor substrate and the robotic substrate handling blade has been greatly reduced by the use of specialized materials either as the principal material of construction for the semiconductor substrate handling blade, or as a coating upon the surface of the wafer handling blade. In particular, the specialized material must exhibit the desired stiffness at temperatures in excess of about 450. degree. C. ; the specialized material must also have an abrasion resistant surface which does not produce particulates when rubbed against the semiconductor substrate. The abrasion resistant surface needs to be very smooth, having a surface finish of less than 1. 0 micro inch, and preferably less than 0. 2 micro inch.

Robot Blade For Handling Of Semiconductor Substrates

US Patent:
6199927, Mar 13, 2001
Filed:
Jan 21, 1999
Appl. No.:
9/294440
Inventors:
Behzad Shamlou - San Jose CA
Wen Chiang Tu - Mountain View CA
Xuyen Pham - Fremont CA
Yu Chang - San Jose CA
Daniel O. Clark - Pleasanton CA
Shun Wu - Cupertino CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
B25J 1506
B65G 4907
US Classification:
294 641
Abstract:
The amount of particulate contamination produced due to rubbing between a semiconductor substrate and the robotic substrate handling blade has been greatly reduced by the use of specialized materials either as the principal material of construction for the semiconductor substrate handling blade, or as a coating upon the surface of the substrate handling blade. In particular, the specialized material must exhibit the desired stiffness at temperatures in excess of about 450. degree. C. ; the specialized material must also have an abrasion resistant surface which does not produce particulates when rubbed against the semiconductor substrate. The abrasion resistant surface needs to be very smooth, having a surface finish of less than 1. 0 micro inch, and preferably less than 0. 2 micro inch.

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