William Tze Kao, Age 47Los Altos, CA

William Kao Phones & Addresses

Los Altos Hills, CA

Brooklyn, NY

750 Dearborn St, Chicago, IL 60610 (312) 335-0278

440 Wabash Ave, Chicago, IL 60611

New York, NY

Durham, NC

Kansas City, MO

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Work

Address: 1150 Lake St, Roselle, IL 60172 Specialities: Dentist

Mentions for William Tze Kao

Career records & work history

Medicine Doctors

William Kao

Specialties:
Urology
Work:
Kaiser Permanente Largo Medical Center
1221 Mercantile Ln STE 403, Upper Marlboro, MD 20774
(301) 618-5500 (phone) (301) 618-5714 (fax)
Education:
Medical School
Virginia Commonwealth University SOM
Graduated: 2004
Procedures:
Circumcision, Cystourethroscopy, Kidney Stone Lithotripsy, Prostate Biopsy, Transurethral Resection of Prostate, Bladder Repair, Cystoscopy, Nephrectomy, Urinary Flow Tests, Vaginal Repair, Vasectomy
Conditions:
Bladder Cancer, Kidney Cancer, Benign Prostatic Hypertrophy, Calculus of the Urinary System, Erectile Dysfunction (ED), Male Infertility, Prostate Cancer, Prostatitis, Testicular Cancer, Undescended and Retractile Testicle, Urinary Incontinence, Urinary Tract Infection (UT)
Languages:
English, Spanish
Description:
Dr. Kao graduated from the Virginia Commonwealth University SOM in 2004. He works in Upper Marlboro, MD and specializes in Urology. Dr. Kao is affiliated with Holy Cross Hospital and Medstar Washington Hospital Center.
William Kao Photo 1

William Wan Kao

Specialties:
Urology
William Kao Photo 2

William Chishon Kao, Roselle IL

Specialties:
Dentist
Address:
1150 Lake St, Roselle, IL 60172

William Kao resumes & CV records

Resumes

William Kao Photo 41

Administrator

Industry:
Wholesale
Work:
Got Shades International Inc
Administrator
William Kao Photo 42

William Kao

William Kao Photo 43

William Kao

Location:
United States
William Kao Photo 44

Independent Financial Services Professional

Location:
Greater New York City Area
Industry:
Financial Services

Publications & IP owners

Us Patents

Method, System, And Article Of Manufacture For Implementing Metal-Fill With Power Or Ground Connection

US Patent:
7231624, Jun 12, 2007
Filed:
Nov 19, 2002
Appl. No.:
10/300544
Inventors:
Thanh Vuong - Milpitas CA, US
William H. Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 13, 716 14, 716 15, 716 16
Abstract:
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Method, System, And Article Of Manufacture For Implementing Metal-Fill On An Integrated Circuit

US Patent:
7287324, Oct 30, 2007
Filed:
Nov 19, 2002
Appl. No.:
10/300722
Inventors:
Thanh Vuong - Milpitas CA, US
William H. Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
H05K 3/02
US Classification:
29846, 29825, 29852
Abstract:
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Place And Route Tool That Incorporates A Metal-Fill Mechanism

US Patent:
7328419, Feb 5, 2008
Filed:
Nov 19, 2002
Appl. No.:
10/300715
Inventors:
Thanh Vuong - Milpitas CA, US
William H. Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 11, 716 8, 716 9, 716 10
Abstract:
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Method, System, And Article Of Manufacture For Reducing Via Failures In An Integrated Circuit Design

US Patent:
7574685, Aug 11, 2009
Filed:
Apr 24, 2007
Appl. No.:
11/739622
Inventors:
Xiaopeng Dong - San Jose CA, US
Inhwan Seo - Fremont CA, US
William Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Gary Nunn - Los Gatos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 11, 716 5
Abstract:
An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.

Method And System For Implementing Metal Fill

US Patent:
7661078, Feb 9, 2010
Filed:
Feb 28, 2005
Appl. No.:
11/069759
Inventors:
David C. Noice - Palo Alto CA, US
William Kao - Fremont CA, US
Inhwan Seo - Fremont CA, US
Xiaopeng Dong - San Jose CA, US
Gary W. Nunn - Los Gatos CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/45
US Classification:
716 4, 716 5
Abstract:
Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.

Method And Apparatus For Substrate Noise Aware Floor Planning For Integrated Circuit Design

US Patent:
7865850, Jan 4, 2011
Filed:
Feb 26, 2008
Appl. No.:
12/037843
Inventors:
William Kao - Fremont CA, US
Xiaopeng Dong - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 8, 716 10, 703 14, 703 15
Abstract:
A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon noise sensitive circuits.

Method, System, And Article Of Manufacture For Implementing Metal-Fill With Power Or Ground Connection

US Patent:
7865858, Jan 4, 2011
Filed:
Jun 8, 2007
Appl. No.:
11/760711
Inventors:
Thanh Vuong - Milpitas CA, US
William H. Kao - Fremont CA, US
David C. Noice - Palo Alto CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 12, 716 2, 716 14, 716 19
Abstract:
Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Method And System For Implementing Timing Aware Metal Fill

US Patent:
8161425, Apr 17, 2012
Filed:
Apr 19, 2006
Appl. No.:
11/407873
Inventors:
David Noice - Palo Alto CA, US
Gary Nunn - Los Gatos CA, US
Inhwan Seo - Fremont CA, US
William Kao - Fremont CA, US
Xiaopeng Dong - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 55, 716 51, 716 52, 716 53, 716 54, 716 56, 430 5, 430 30
Abstract:
An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

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