William M Mcgonagle Deceased38 Woodridge Dr, Windsor Locks, CT 06096

William Mcgonagle Phones & Addresses

38 Woodridge Dr, Windsor Locks, CT 06096

1101 Meadowview Dr, East Windsor, CT 06088

1310 Berlin Tpke, Wethersfield, CT 06109

Hartford, CT

Dunstable, MA

Mentions for William M Mcgonagle

William Mcgonagle resumes & CV records

Resumes

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William Mcgonagle

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William Mcgonagle

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Customer Service Engineer At Tektronix

Location:
Groraum Boston und Umgebung
Industry:
Telekommunikation
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Machinist At Haynes Corp

Location:
Naples und Umgebung, Florida
Industry:
Eisenbahnbau
William Mcgonagle Photo 26

Table Games Dealer At Ipcasino

Location:
Biloxi, Mississippi und Umgebung
Industry:
Unterhaltung

Publications & IP owners

Wikipedia

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William Mcgagle

William Loren McGonagle (November 19, 1925 March 3, 1999) was a United States Naval officer who received the Medal of Honor for his actions while in ...

Us Patents

Low-Light-Level Imaging And Image Processing

US Patent:
5880777, Mar 9, 1999
Filed:
Apr 15, 1996
Appl. No.:
8/632746
Inventors:
Eugene D. Savoye - Concord MA
Allen M. Waxman - Newton MA
Robert K. Reich - Chelmsford MA
Barry E. Burke - Lexington MA
James A. Gregory - Sudbury MA
William H. McGonagle - Dunstable MA
Andrew H. Loomis - Chelmsford MA
Bernard B. Kosicki - Acton MA
Robert W. Mountain - Newburyport MA
Alan N. Gove - Brookline MA
David A. Fay - Somerville MA
James E. Carrick - Natick MA
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H04N 5225
US Classification:
348217
Abstract:
An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B. The output image frame sequence is characterized by noise-limited resolution of at least a minimum number, N. sub. M, of line pairs per millimeter, referred to the charge-coupled imaging device pixel array, in an imaged scene as a function of illuminance of the input light impinging the charge-coupled imaging device pixels.

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