Xiaozhou Hu resumes & CV records
Resumes
![Xiaozhou Hu Photo 10 Xiaozhou Hu Photo 10](/img/not-found.png)
Physical Design Verification Engineer
Location:
San Jose, CA
Industry:
Semiconductors
Work:
Intel Corporation
Physical Design Verification Engineer Marvell Semiconductor Sep 1999 - Jul 2015
Staff Cad Level One Communications Mar 1996 - Sep 1999
Senior Physical Mask Layout Design Engineer Xilinx Mar 1996 - Sep 1999
Physical Design Verification Engineer
Physical Design Verification Engineer Marvell Semiconductor Sep 1999 - Jul 2015
Staff Cad Level One Communications Mar 1996 - Sep 1999
Senior Physical Mask Layout Design Engineer Xilinx Mar 1996 - Sep 1999
Physical Design Verification Engineer
Skills:
Semiconductors, Verilog, Soc, Asic, Ic, Icc, Virtuoso