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Ying Te He, Age 56Bellevue, WA

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Known as:
Ying W He Ying E He Etux Ying He Ying H Tang Max Moffitt

Ying He Phones & Addresses

Bellevue, WA

Kirkland, WA

Los Altos, CA

Reno, NV

1861 Mark Twain St, Palo Alto, CA 94303

Sunnyvale, CA

Mountain View, CA

San Jose, CA

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Work

Company: Century 21 Realty Alliance Address: San Francisco, CA Phones: (415) 860-8320 (Phone)

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Career records & work history

Real Estate Brokers

Ying He Photo 1

Ying He, San Francisco CA - Agent

Work:
Century 21 Realty Alliance
San Francisco, CA
(415) 860-8320 (Phone)
License #01255995

License Records

Ying He

Licenses:
License #: 31592 - Active
Issued Date: Nov 8, 2013
Renew Date: Dec 1, 2015
Expiration Date: Nov 30, 2017
Type: Certified Public Accountant

Ying He resumes & CV records

Resumes

Ying He Photo 40

Medical Technologist

Location:
Bellevue, WA
Industry:
Hospital & Health Care
Work:
Interpath Laboratory, Inc
Medical Technologist
Education:
University of Washington 2013 - 2016
Master of Science, Masters Nanchang University 2008 - 2013
Bachelors, Bachelor of Science
Skills:
Healthcare, Hospitals, Clinical Research, Healthcare Management, Healthcare Information Technology, Microsoft Office, Electronic Medical Record, Microsoft Excel, Leadership, Medical Terminology
Ying He Photo 41

Ying He

Ying He Photo 42

Ying He

Ying He Photo 43

Ying He

Ying He Photo 44

Ying He

Publications & IP owners

Us Patents

Floorplan Visualization Method Using Gate Count And Gate Density Estimations

US Patent:
7197735, Mar 27, 2007
Filed:
Dec 15, 2004
Appl. No.:
11/012741
Inventors:
Gregor J. Martin - Mountain View CA, US
Ying Chun He - Milpitas CA, US
Grant Lindberg - Pleasanton CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 8, 716 11, 716 12
Abstract:
A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.

Allocation Of Upstream Bandwidth In An Ethernet Passive Optical Network

US Patent:
7245628, Jul 17, 2007
Filed:
Jul 9, 2002
Appl. No.:
10/192835
Inventors:
Haixing Shi - Santa Clara CA, US
Ying He - Palo Alto CA, US
International Classification:
H04J 3/16
US Classification:
370437
Abstract:
A passive optical network (PON) in accordance with the invention uses a superframe having a number of subframes arranged in a two-dimensional array, wherein for normal data transfer subframes are allocated to each optical network unit (ONU) column by column, left to right, and within each column subframes are allocated from top to the bottom. Initially, for ranging, at least two subframes are allocated to an ONU, adjacent to a diagonal of the superframe (which may go from the top left corner of the superframe to the bottom right corner, or alternatively from the top right corner to the bottom left corner). In some embodiments, instead of allocating subframes column by column, the subframes are evenly spaced apart from one another, and conflicts with a previous allocation are resolved by adjustment, and optionally an evaluation function may be used to find an optimal allocation.

Enabling Efficient Design Reuse In Platform Asics

US Patent:
7299446, Nov 20, 2007
Filed:
Aug 16, 2005
Appl. No.:
11/204669
Inventors:
Ying Chun He - Milpitas CA, US
Gregor J. Martin - Mountain View CA, US
Grant Lindberg - Pleasanton CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 18, 716 1, 716 4, 716 11
Abstract:
A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.

Resource Estimation For Design Planning

US Patent:
7464345, Dec 9, 2008
Filed:
Aug 1, 2005
Appl. No.:
11/194299
Inventors:
Gregor J. Martin - Mountain View CA, US
Grant Lindberg - Pleasanton CA, US
Ying Chun He - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 2, 716 3, 716 18
Abstract:
A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step generally involves receiving user input of estimated design information for the second portion of the integrated circuit design. A third step generally involves automatically generating one or more representative blocks representing the second portion of the integrated circuit design based on the user input. The one or more representative blocks may be generated having substantially equivalent size and characteristics to one or more actual blocks developed for the second portion of the integrated circuit design.

Ip Placement Validation

US Patent:
7469398, Dec 23, 2008
Filed:
Aug 16, 2005
Appl. No.:
11/204670
Inventors:
Gregor J. Martin - Mountain View CA, US
Ying Chun He - Milpitas CA, US
Grant Lindberg - Pleasanton CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
US Classification:
716 10, 716 2, 716 5, 716 11
Abstract:
A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information for an intellectual property (IP) block to be placed on a platform application specific integrated circuit, (B) extracting device data for the platform application specific integrated circuit and (C) determining one or more valid placement locations for the intellectual property (IP) block based upon the IP recorded information and the device data.

I/O Planning With Lock And Insertion Features

US Patent:
7543261, Jun 2, 2009
Filed:
Apr 27, 2005
Appl. No.:
11/115798
Inventors:
Grant Lindberg - Pleasanton CA, US
Gregor J. Martin - Mountain View CA, US
David Asson - Sisters OR, US
Ying Chun He - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 9/455
G06F 17/50
US Classification:
716 11
Abstract:
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.

I/O Planning With Lock And Insertion Features

US Patent:
8099708, Jan 17, 2012
Filed:
Apr 30, 2009
Appl. No.:
12/432996
Inventors:
Grant Lindberg - Pleasanton CA, US
Gregor J. Martin - Mountain View CA, US
David Asson - Sisters OR, US
Ying Chun He - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 17/50
G06F 15/04
US Classification:
716139
Abstract:
A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.

Comprehensive, Relevant, And Dynamic Data Searching In A Virtualization Environment

US Patent:
2011021, Sep 1, 2011
Filed:
May 20, 2010
Appl. No.:
12/783621
Inventors:
Liang CUI - Beijing, CN
Hailing XU - Peking, CN
Ying HE - Palo Alto CA, US
Assignee:
VMware, Inc. - Palo Alto CA
International Classification:
G06F 17/30
G06F 9/455
G06F 21/00
US Classification:
707711, 718 1, 707741, 726 1, 707E17002, 707E17108, 707E17032, 707769
Abstract:
A method includes indexing data and/or metadata in online virtual machines (VMs), offline VMs, virtual applications, and/or snapshots thereof on one or more host server(s) in a virtualization environment through a search architecture in the virtualization environment. The online VMs are VMs that are powered on, and the offline VMs are VMs that are powered off. The method also includes maintaining a database of the indexed data and/or metadata in the online VMs, the offline VMs, the virtual applications, and/or the snapshots thereof to enable a comprehensive search result to a search query through the search architecture. The database is associated with the search architecture.

Possible Relatives

Dayong He  Da M He  Emily F He  Feng Q He  Frank H He  Guang M He  Henry C He  Ying B Mei  Ying J Kuo  Ying L Meng 

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