Yungcheng Lo, Age 60Cupertino, CA

2017033, Nov 23, 2017

Jan 31, 2017

15/421109

- Gyeonggi-do, KR
Yungcheng Thomas Lo - Cupertino CA, US

G06F 3/06
G06F 11/07
G06F 11/14

A flash memory device includes a flash memory configured to store a plurality of pages and a control circuit coupled to the flash memory. The control circuit is configured to retrieve data from a page of the flash memory, determine a number of zeroes or ones of the retrieved data, determine whether the number is between a first value and a second value, and determine that the retrieved data has one or more errors based on determining that the number is not between the first value and the second value.

2017032, Nov 16, 2017

May 15, 2017

15/595636

- San Jose CA, US
Yungcheng LO - Cupertino CA, US

G06F 12/02
G11C 16/06

A semiconductor memory system and an operating method thereof include a controller configured to perform macro management; and a memory device including Nand pages, counters, a self-management component, and devoted memories, wherein the memory device is coupled and controlled by the controller, the Nand pages contains data corresponding to commands received from the controller, the counters are configured to track operation information corresponding to the Nand pages in accordance with the commands, the devoted memories are configured to record recovery information, and the self-management component configured to perform micro management in accordance at least in part with the operation information or the recovery information.

2017032, Nov 16, 2017

May 15, 2017

15/595592

- San Jose CA, US
Yungcheng LO - Cupertino CA, US

G06F 12/0831
G06F 12/0868
G06F 12/0813
G06F 12/0897
G06F 3/06
G06F 12/0866
G11C 16/10
G06F 12/02

A semiconductor memory system and an operating method thereof include a controller; and a memory device including a memory page manager, Nand pages, and multiple cache pages, wherein the Nand pages include current Nand pages and next Nand pages, wherein the current Nand pages is corresponding to a read command received from the controller, the memory page manager is configured to manage correlation of the Nand pages and the multiple cache pages, predict next Nand pages in accordance at least in part with the read command, the current Nand pages, or a combination thereof, and send the Nand pages to the controller, and the multiple cache pages contain pages loaded from the Nand pages.

2017033, Nov 16, 2017

May 15, 2017

15/595664

- San Jose CA, US
Yungcheng LO - Cupertino CA, US

G11C 8/12
G06F 11/30
G06F 11/16

A semiconductor memory system and an operating method thereof include a memory device; and a memory controller including a sequence generator, a sequence analyzer, and a processor coupled to the memory device and containing instructions executed by the processor, and configured to generate a sequence by the sequence generator, wherein the sequence comprises a sequence of digital data, write the sequence associated with a user data to the memory device, read out a read data including the sequence and the associated user data, analyze the sequence to understand characters of the read data and create analysis result by the sequence analyzer, identify an optimal threshold voltage in accordance with the analysis result, and provide the optimal threshold voltage to an ECC engine.

2017029, Oct 12, 2017

Jan 31, 2017

15/421113

- Gyeonggi-do, KR
Yungcheng Thomas Lo - Cupertino CA, US

G06F 3/06
G11C 16/08

A flash memory device includes a flash memory having a plurality of blocks, each block having a plurality of pages, and a control circuit configured to receive a command, decode the received command to determine whether the command is a last written page command, upon determining that the command is the last written page command, select a block of the plurality of blocks, and perform a number of iterations. Each of the iterations includes obtain a measurement of a signal level of a page in the selected block, compare the signal level with a predetermined threshold value, determine whether the page is an erased page based on a comparison result, upon determining that the page is an erased page, save an address associated with the erased page and output the address of the erased page, and upon determining that the page is not an erase page, perform a next iteration.

2017029, Oct 12, 2017

Jan 31, 2017

15/421112

- Gyeonggi-do, KR
Yungcheng Thomas Lo - Cupertino CA, US

G06F 3/06
G11C 16/16
G11C 16/04
G11C 16/10

A flash memory device includes a flash memory comprising a plurality of pages for storing data, a control circuit configured to select a page of the plurality of pages in response to a received command, an accumulator configured to obtain a signal value of the selected page, and a comparator configured to compare the signal value with a predetermined value. The control circuit generates an indication signal indicative of a state of the selected page based on a comparison result.