Zuhua Zhu Deceased11740 National Blvd, Los Angeles, CA 90064

6406795, Jun 18, 2002

Oct 25, 1999

09/426273

Wen-Yen Hwang - Sugar Land TX
Yucai Zhou - Ithaca NY
Zuhua Zhu - Ithaca NY
Yu-Hwa Lo - San Diego CA

Applied Optoelectronics, Inc. - Sugar Land TX

B32B 1504

428457, 428620, 428700, 257 9, 257183

A compliant substrate for the formation of semiconductor devices includes a crystalline base layer and a thin-film crystalline layer on and loosely bonded to the base layers. The thin-film layer has a high degree of lattice flexibility. A compliant substrate for formation of semiconductor devices may also include a crystalline base layer, and, on the base layer, a thin film layer having a lattice constant different from the lattice constant of the base layer. A method for formation of a compliant substrate for formation of semiconductor devices includes forming a thin film layer on a first substrate, bonding a first surface of the thin film layer to a surface of a second substrate having a lattice constant different from the lattice constant of the thin film layer either with or without twist bonding, and removing the first substrate to expose a second surface of the thin film layer.

6589805, Jul 8, 2003

Mar 26, 2002

10/106991

Zuhua Zhu - San Jose CA
Shih-Yuan Wang - Palo Alto CA

Gazillion Bits, Inc. - San Jose CA

H01L 21302

438 22, 438 42, 438 47, 438718, 438739

A vertical cavity surface emitting laser (VCSEL) structure and fabrication method therefor are described in which a subsurface air, gas, or vacuum current confinement method is used to restrict the area of electrical flow in the active region. Using vertical hollow shafts to access a subsurface current confinement layer, a selective lateral etching process is used to form a plurality of subsurface cavities in the current confinement layer, the lateral etching process continuing until the subsurface cavities laterally merge to form a single subsurface circumferential cavity that surrounds a desired current confinement zone. Because the subsurface circumferential cavity is filled with air, gas, or vacuum, the stresses associated with oxidation-based current confinement methods are avoided. Additionally, because the confinement is achieved by subsurface cavity structures, overall mechanical strength of the current-confining region is maintained.

6836357, Dec 28, 2004

Dec 4, 2001

10/006435

Shih-Yuan Wang - Palo Alto CA
Miao Zhu - San Jose CA
Zuhua Zhu - San Jose CA
Haiqing Wei - Sunnyvale CA
Saif M. Islam - Santa Clara CA

Gazillion Bits, Inc. - San Jose CA

H01S 300

359344

A semiconductor optical amplifier (SOA) apparatus and related methods are described. The SOA comprises a signal waveguide for guiding an optical signal along a signal path, and further comprises one or more laser cavities having a gain medium lying outside the signal waveguide, the gain medium being sufficiently close to the signal waveguide such that, when the gain medium is pumped with an excitation current, the optical signal traveling down the signal waveguide is amplified by an evanescent coupling effect with the laser cavity. When the gain medium is sufficiently pumped to cause lasing action in the laser cavity, gain-clamped amplification of the optical signal is achieved. Additional features relating to segmented laser cavities, separate pumping of laser cavity segments, DFB/DBR gratings, current profiling to improve ASE noise performance, coupled-cavity lasers, avoidance of injection locking effects, manipulation of gain curve peaks, integration with a tunable vertical cavity coupler, integration with a photodetector, integration with an RZ signal modulator, and other described features may be used with the evanescent coupling case or with an SOA having a laser cavity gain medium that is coextensive with the gain medium of the signal waveguide.

6876687, Apr 5, 2005

Jun 23, 2003

10/602139

Zuhua Zhu - San Jose CA, US
Shih-Yuan Wang - Palo Alto CA, US

Gazillion Bits, Inc. - San Jose CA

H01S005/00

372 45, 372 46

A vertical cavity surface emitting laser (VCSEL) structure and fabrication method therefor are described in which a subsurface air, gas, or vacuum current confinement method is used to restrict the area of electrical flow in the active region. Using vertical hollow shafts to access a subsurface current confinement layer, a selective lateral etching process is used to form a plurality of subsurface cavities in the current confinement layer, the lateral etching process continuing until the subsurface cavities laterally merge to form a single subsurface circumferential cavity that surrounds a desired current confinement zone. Because the subsurface circumferential cavity is filled with air, gas, or vacuum, the stresses associated with oxidation-based current confinement methods are avoided. Additionally, because the confinement is achieved by subsurface cavity structures, overall mechanical strength of the current-confining region is maintained.

6878958, Apr 12, 2005

Mar 26, 2002

10/106929

Zuhua Zhu - San Jose CA, US

Gazillion Bits, Inc. - San Jose CA

H01L029/06
H01L031/072
H01L031/109
H01L031/0328
H01L031/0336

257 12, 257 37

A vertical cavity surface-emitting laser (VCSEL) structure and related fabrication methods are described, the VCSEL comprising amorphous dielectric distributed Bragg reflectors (DBRs) while also being capable of fabrication in a single-growth process. Beginning with a substrate such as InP, a first amorphous dielectric DBR structure is deposited thereon, but is limited in width such that some substrate material remains uncovered by the dielectric material. A lateral overgrowth layer is then formed by epitaxially growing material such as InP onto the substrate, the lateral overgrowth layer eventually burying the dielectric DBR structure as well as the previously-uncovered substrate material. Active layers may then be epitaxially grown on the lateral overgrowth layer, and a top dielectric DBR may be deposited thereon using conventional techniques. To save vertical space between DBRs, the first DBR may be deposited in a non-reentrant well formed in the surface of a substrate.

7265898, Sep 4, 2007

Dec 27, 2004

11/024319

Shih-Yuan Wang - Palo Alto CA, US
Miao Zhu - San Jose CA, US
Zuhua Zhu - San Jose CA, US
Haiqing Wei - Sunnyvale CA, US
Saif M. Islam - Santa Clara CA, US

Gazillion Bits, Inc. - San Jose CA

H01S 3/00

359344, 359337

A semiconductor optical amplifier (SOA) apparatus and related methods are described. The SOA comprises a signal waveguide for guiding an optical signal along a signal path, and further comprises one or more laser cavities having a gain medium lying outside the signal waveguide, the gain medium being sufficiently close to the signal waveguide such that, when the gain medium is pumped with an excitation current, the optical signal traveling down the signal waveguide is amplified by an evanescent coupling effect with the laser cavity. When the gain medium is sufficiently pumped to cause lasing action in the laser cavity, gain-clamped amplification of the optical signal is achieved. Additional features relating to segmented laser cavities, separate pumping of laser cavity segments, DFB/DBR gratings, current profiling to improve ASE noise performance, coupled-cavity lasers, avoidance of injection locking effects, manipulation of gain curve peaks, integration with a tunable vertical cavity coupler, integration with a photodetector, integration with an RZ signal modulator, and other described features may be used with the evanescent coupling case or with an SOA having a laser cavity gain medium that is coextensive with the gain medium of the signal waveguide.

2001004, Nov 22, 2001

Feb 10, 1999

09/247413

YU-HWA LO - ITHACA NY, US
ZUHUA ZHU - ITHACA NY, US

C30B001/00
H01L021/00
H01L021/84

117/004000, 438/162000

A method for forming low defect density epitaxial layers on lattice-mismatched substrates includes confining dislocations through interactions between the dislocations and the stress field in the epitaxial layer. This method is applicable to any heteroepitaxial material systems with any degree of lattice mismatch. The method includes choosing the desired epilayer and the top substrate layer for epitaxial growth, determining the lattice constant and thermal expansion coefficient of the final epilayer and the top substrate layer, bonding an additional substrate layer under the top substrate layer to form a composite substrate so that the desired epilayer has negative (positive) or zero thermal mismatch to the composite substrate if the lattice mismatch between the epilayer and the top substrate layer is positive (negative), and choosing a buffer layer to be deposited before the desired epilayer which is lattice matched to the epilayer. The chosen buffer layer should have a positive (negative) thermal mismatch to the entire substrate if the lattice mismatch is also positive (negative).

2001005, Dec 20, 2001

Mar 5, 2001

09/800401

Zuhua Zhu - Ithaca NY, US
Yu-Hwa Lo - Ithaca NY, US

Nova Crystals, Inc.

B23K031/02

228/121000, 228/234100

A method of semiconductor eutectic alloy metal (SEAM) technology for integration of heterogeneous materials and fabrication of compliant composite substrates takes advantage of eutectic properties of alloys. Suband Subare used to represent the two heterogeneous materials to be bonded or composed into a compliant composite substrate. For the purpose of fabricating compliant composite substrate, the first substrate material (Sub) combines with the second substrate material (Sub) to form a composite substrate that controls the stress in the epitaxial layers during cooling. The second substrate material (Sub) controls the stress in the epitaxial layer grown thereon so that it is compressive during annealing. A joint metal (JM) with a melting point of Tis chosen to offer variable joint stiffness at different temperatures. JM and Subform a first eutectic alloy at a first eutectic temperature Twhile JM and Subform a second eutectic alloy at a second eutectic temperature T. Tand Tare the melting points of Suband Subrespectively The following condition should be met: T, T T T, T. After cleaning of Suband SubJM is deposited on the bonding sides of Suband SubAfter preliminary bonding by applying force to press the bonding surfaces together at room temperature, high temperature bonding is subsequently performed, during which the temperature is ramped up to a temperature equal to or higher than T. During cooling, JM solidifies first, after which two eutectic alloys solidify.