Arunangshu A Kundu, Age 594574 Grimsby Dr, San Jose, CA 95130

6750674, Jun 15, 2004

Oct 2, 2002

10/264288

Arunangshu Kundu - San Jose CA
Jerome Fron - Palo Alto CA

Actel Corporation - Mountain View CA

H03K 19173

326 38, 326 41

A field programmable gate array comprising a plurality of logic modules each logic module having two clusters, said logic modules arranged in rows and columns. The logic module clusters having a plurality of receiver components, a plurality of transmitter components, at least one buffer module, and at least one sequential logic components. Each logic module also comprises at least one left combinatorial logic unit having a carry-in input and carry-out output and at least one right combinatorial logic unit having a carry-in input and carry-out output adjacent to said left combinatorial logic unit. The carry-out output of the left combinatorial unit is hardwired to the carry-in input of said right combinatorial logic unit providing dedicated carry-in/carry-out logic circuitry.

6751723, Jun 15, 2004

Sep 2, 2000

09/654237

Arunangshu Kundu - San Jose CA
Arnold Goldfein - Sunnyvale CA
William C. Plants - Sunnyvale CA
David Hightower - Freemont CA

Actel Corporation - Mountain View CA

G06F 1580

712 36, 712 10, 712 17, 712 18, 712 33, 712 35, 716 16

An system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

6825690, Nov 30, 2004

May 28, 2003

10/448258

Arunangshu Kundu - San Jose CA

Actel Corporation - Mountain View CA

H03K 19177

326 41, 326 40, 326 47, 326101, 327141, 327144, 327150, 327156

A clock tree distribution network for a field programmable gate array comprises an interface that has a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array that has programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from between a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network that selects a signal from between a clock signal from the interface and a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

6838902, Jan 4, 2005

May 28, 2003

10/448259

Daniel Elftmann - Livermore CA, US
Theodore Speers - San Jose CA, US
Arunangshu Kundu - San Jose CA, US

Actel Corporation - Mountain VIew CA

H03K 19177

326 40, 326 41, 36523003, 36518901, 365 63, 365233

The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks.

6867615, Mar 15, 2005

May 30, 2003

10/452764

William C. Plants - Sunnyvale CA, US
Arunangshu Kundu - San Jose CA, US

Actel Corporation - Mountain View CA

H03K019/177
G06F007/38

326 40, 326 41, 326 47

A field programmable gate array having a plurality of input/output pads and dedicated input/output first-in/first-out memory. The dedicated input/output first-in/first-out memory comprising a plurality of input/output clusters coupled to the input/output pads of the field programmable gate array and a plurality of input/output block controllers coupled to said input/output clusters.

6891396, May 10, 2005

Dec 27, 2002

10/330672

Arunangshu Kundu - San Jose CA, US
Eric Sather - Palo Alto CA, US
William C. Plants - Sunnyvale CA, US

Actel Corporation - Mountain View CA

H03K019/177
H01L025/00

326 41, 326 38

The apparatus comprises a repeatable non-uniform segmented routing architecture in a field programmable gate array having a plurality of sets of routing tracks having a first and last track position proceeding in a first direction and having at least one programmable element and at least one direct address device. The tracks are partitioned into uniform lengths and a track in the last position crosses over to a track in the first position immediately prior to said partition. The apparatus of the present system also has a plurality of sets of routing tracks having a first and last track position proceeding in a second direction. The tracks proceeding in the second direction have at least one programmable element and direct address device, wherein the tracks are partitioned into uniform lengths and said last track position crosses over to a first track position immediately prior to said partition.

6946871, Sep 20, 2005

Dec 18, 2002

10/323613

Arunangshu Kundu - San Jose CA, US
Venkatesh Narayanan - San Jose CA, US
John McCollum - Saratoga CA, US
William C. Plants - Sunnyvale CA, US

Actel Corporation - Mountain View CA

H03K019/177

326 41, 326 47

A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

6976185, Dec 13, 2005

Nov 25, 2003

10/722636

William C. Plants - Campbell CA, US
Nikhil Mazumder - San Jose CA, US
Arunangshu Kundu - San Jose CA, US
James Joseph - Monument CO, US
Wayne W. Wong - Sunnyvale CA, US

Actel Corporation - Mountain View CA

G06F001/08

713500

A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.