Inventors:
- San Diego CA, US
Wesley James Holland - La Jolla CA, US
Bohuslav Rychlik - San Diego CA, US
Andrew Edmund Turner - San Diego CA, US
Jeffrey Shabel - San Diego CA, US
Simon Peter William Booth - San Diego CA, US
Christopher Koob - Round Rock TX, US
Wisnu Wurjantara - Toronto, CA
David Hansen - Calgary, CA
Ron Lieberman - Austin TX, US
Daniel Palermo - Austin TX, US
Colin Sharp - Cardiff CA, US
Hao Liu - San Diego CA, US
International Classification:
G06F 12/0893
G06F 12/06
G06F 3/06
H03M 7/30
Abstract:
An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.
