Gopalan U Ramanujam, Age 6714231 NW Tradewind St, Portland, OR 97229

6618046, Sep 9, 2003

Sep 29, 2000

09/675610

Ganapati N. Srinivasa - Portland OR
Gopalan Ramanujam - Hillsboro OR
Glenn M. Lewis - Newport Beach CA
Calvin J. Lin - Hillsboro OR
Jeffrey A. Larson - Beaverton OR
Arunachalam S. Prakash - Portland OR

Intel Corporation - Santa Clara CA

G06T 1700

345418, 705400

A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

6897857, May 24, 2005

May 22, 2003

10/444855

Ganapati N. Srinivasa - Portland OR, US
Gopalan Ramanujam - Hillsboro OR, US
Glenn M. Lewis - Newport Beach CA, US
Calvin J. Lin - Hillsboro OR, US
Jeffrey A. Larson - Beaverton OR, US
Arunachalam S. Prakash - Portland OR, US

Intel Corporation - Santa Clara CA

G06T015/00

345415

A rendering cost estimation method is provided for generating a rendering cost estimate that that is sufficiently close to an actual rendering cost that would be incurred if computer-generated images were actually rendered from a computer-graphics model. A plurality of cost factors that affect the actual rendering cost are identified. Representative information, including rendering cost estimation parameters that adequately characterize the cost factors, is derived from the computer-graphics model. The estimation parameters are combined with rendering cost estimation relationships that express the affect of the cost factors on the rendering cost. A rendering cost estimate is generated based on the estimation parameters derived from the computer-graphics model and the estimation relationships.

7360220, Apr 15, 2008

Oct 31, 2002

10/284602

Gopalan Ramanujam - Portland OR, US
Narendra S. Nayak - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 9/46

718107, 718104

Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two different software segments. One of the software segments is coded to perform the algorithm using primarily a first processor resource (e. g. , a floating point unit). Another software segment is coded to perform the same algorithm using a primarily a second processor resource (e. g. , an integer execution unit). A workload requiring execution of the algorithm is allocated to the threads in a balanced manner (e. g. , faster code segments are given more of the workload). The threads use different processor resources, therefore the threads are able to execute in parallel in an efficient manner. When each of the threads completes execution, the results may be synchronized.

7899855, Mar 1, 2011

Sep 8, 2003

10/658612

Gopalan Ramanujam - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 7/00

708204

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

8533244, Sep 10, 2013

Jan 7, 2011

12/986924

Gopalan Ramanujam - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 7/00

708204

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

2006029, Dec 28, 2006

Jun 28, 2005

11/170003

Gopalan Ramanujam - Portland OR, US
Vasanth Tovinkere - Portland OR, US

G06F 9/44

717131000

A method and system to identify serial code regions in applications is described. The method includes instrumenting an application's code at loop entry points and loop exit points and gathering data about a plurality of loops in the application. The data may include the amount of time spent in each loop, the number of times each loop is executed, and/or loop hierarchies. A list of the loops may be displayed based on the gathered data. One or more of the plurality of loops may be selected for threading based on the gathered data. Directives may then be inserted into the application's code to thread one or more of the plurality of loops. The threaded loops may then be simulated and any resulting errors may be displayed.

2013002, Jan 24, 2013

Sep 24, 2012

13/625073

Gopalan Ramanujam - Portland OR, US

G06F 9/30

712208, 712E09028

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

2013002, Jan 24, 2013

Sep 24, 2012

13/625085

Gopalan Ramanujam - Portland OR, US

G06F 9/30
G06F 9/312

712208, 712E09028, 712E09033

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.