Harinder S Singh, Age 456331 Littlefield Ct, Centreville, VA 20121

2018015, May 31, 2018

Oct 31, 2017

15/798778

- San Diego CA, US
Douglas Dahlby - Stone Ridge VA, US
Murali Krishna - San Diego CA, US
Harinder Singh - Saratoga CA, US
Ravi Konda - San Jose CA, US
BalaSubrahmanyam Chintamneedi - San Diego CA, US

G06F 1/32
G06F 12/1009
G06F 13/42
G06F 9/44

The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.

2018015, May 31, 2018

Oct 31, 2017

15/799481

- San Diego CA, US
Douglas Dahlby - Stone Ridge VA, US
Murali Krishna - San Diego CA, US
Harinder Singh - Saratoga CA, US
Ravi Konda - San Jose CA, US
BalaSubrahmanyam Chintamneedi - San Diego CA, US

G06F 1/32
G06F 12/02
G06F 12/1009
G06F 13/42
G06F 9/44
G06F 12/123

The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.

2018015, May 31, 2018

Oct 31, 2017

15/799601

- San Diego CA, US
Douglas Dahlby - Stone Ridge VA, US
Murali Krishna - San Diego CA, US
Harinder Singh - Saratoga CA, US
Ravi Konda - San Jose CA, US
BalaSubrahmanyam Chintamneedi - San Diego CA, US

G06F 1/32
G06N 99/00
G06F 12/128
G06F 12/0862

The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with small periodicity or where there is an intolerance for delays of accessing the code/data.