Jason Miao resumes & CV records
Resumes
Jason Miao
Jason Y Miao, Age 45Auburn Hills, MI
Jason Miao Phones & Addresses
Auburn Hills, MI
329 Tara Dr, Troy, MI 48007 (248) 828-8191
767 Palm Ct, Sunnyvale, CA 94086 (937) 219-1841
San Jose, CA
Mountain View, CA
Santa Clara, CA
Ann Arbor, MI
Mentions for Jason Y Miao
Publications & IP owners
Us Patents
Circuit For Providing A Signal Boost
US Patent:
7504889, Mar 17, 2009
Filed:
Apr 11, 2007
Appl. No.:
11/734185
Inventors:
Jason Y. Miao - San Jose CA, US
Timothy G. Moran - San Jose CA, US
Timothy G. Moran - San Jose CA, US
Assignee:
Finisar Corporaton - Sunnyvale CA
International Classification:
H03F 3/08
US Classification:
330308, 330260
Abstract:
Embodiments disclosed herein relate to an amplifier stage or circuit for providing a signal boost. The circuit includes an emitter-follower pair and a cross coupled differential pair. The cross coupled differential pair provides a feedback signal that provides a boost to a signal output by the emitter follower pair. In some embodiments, a capacitor of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided. In other embodiments, a current source of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided.
Cross-Point Adjustment Circuit
US Patent:
7626439, Dec 1, 2009
Filed:
May 21, 2007
Appl. No.:
11/736263
Inventors:
Jason Y. Miao - San Jose CA, US
Timothy G. Moran - San Jose CA, US
Timothy G. Moran - San Jose CA, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H03K 5/08
US Classification:
327309, 327 79
Abstract:
An amplifier stage or circuit for providing cross-point adjustment. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit also includes a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node that is configured to adjust an amount of current provided to the first and second data signals to create a signal offset. The circuit further includes a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage configured to provide the signal offset at a third and fourth node of the second stage to adjust the cross-point of the first and second signals.
Pre-Emphasis Circuit
US Patent:
7860407, Dec 28, 2010
Filed:
Jul 30, 2007
Appl. No.:
11/830648
Inventors:
Jason Y. Miao - San Jose CA, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H04B 10/06
H04B 10/00
H04B 10/00
US Classification:
398208, 398135, 398136, 398202
Abstract:
An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.
Emi Reduction Stage In A Post-Amplifier
US Patent:
2008007, Mar 27, 2008
Filed:
Apr 5, 2007
Appl. No.:
11/697175
Inventors:
Jason Y. Miao - San Jose CA, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H03F 3/08
US Classification:
330308
Abstract:
An amplifier output stage for reducing Electromagnetic Interference (EMI) that includes an output node and an input node. A first transistor has a base terminal coupled to the input node and has a collector terminal coupled to the output node. A second transistor has a base terminal coupled to an emitter terminal of the first transistor and has a collector terminal coupled to the output node. A third transistor has a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and has an emitter terminal coupled to a current source and to an emitter terminal of the second transistor. A resistor has a first terminal coupled to a base terminal of the third transistor and has a second terminal coupled to the emitter terminal of the first transistor.
Optical Transceiver With Vendor Authentication
US Patent:
2009013, May 28, 2009
Filed:
Nov 26, 2008
Appl. No.:
12/323731
Inventors:
Luke M. Ekkizogloy - Mountain View CA, US
Gerald L. Dybsetter - Scotts Valley CA, US
Jason Y. Miao - San Jose CA, US
Gerald L. Dybsetter - Scotts Valley CA, US
Jason Y. Miao - San Jose CA, US
Assignee:
FINISAR CORPORATION - Sunnyvale CA
International Classification:
H04L 9/32
H04B 10/00
H04L 9/06
H04B 10/00
H04L 9/06
US Classification:
713168, 398135, 380256
Abstract:
An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.
Chip Identification Pads For Identification Of Integrated Circuits In An Assembly
US Patent:
2013014, Jun 13, 2013
Filed:
Mar 21, 2012
Appl. No.:
13/426506
Inventors:
Jason Y. Miao - Sunnyvale CA, US
Georgios Kalogerakis - Mountain View CA, US
Gerald L. Dybsetter - Scotts Valley CA, US
Luke M. Ekkizogloy - Mountain View CA, US
Georgios Kalogerakis - Mountain View CA, US
Gerald L. Dybsetter - Scotts Valley CA, US
Luke M. Ekkizogloy - Mountain View CA, US
Assignee:
FINISAR CORPORATION - Sunnyvale CA
International Classification:
H04B 10/14
H05K 1/18
H05K 1/18
US Classification:
398139, 361748
Abstract:
Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.
Modular Device For An Optical Communication Module
US Patent:
2013014, Jun 13, 2013
Filed:
Dec 6, 2012
Appl. No.:
13/706454
Inventors:
Jason MIAO - Sunnyvale CA, US
Assignee:
FINISAR CORPORATION - Sunnyvale CA
International Classification:
H04B 10/50
US Classification:
398200, 295921
Abstract:
A modular device for an optical communication module configured to be coupled to an optical transmission medium. The modular device may include a first edge and a second edge and N number of electrical circuit channels between the first and second edges. Each electrical circuit channel may include at least one element configured to provide functionality for communicating optical signals through the optical transmission medium. The modular device may also have a width between the first and second edges so that each of the N number of electrical circuit channels of C number of modular devices aligns with one of P number of interface channels of an opto-electrical interface configured to be coupled to the optical transmission medium when C equals P/N and C is a whole number greater than zero.
Integrated Processor And Cdr Circuit
US Patent:
2013029, Nov 7, 2013
Filed:
May 4, 2012
Appl. No.:
13/464286
Inventors:
Jason Y. MIAO - Sunnyvale CA, US
Assignee:
FINISAR CORPORATION - SUNNYVALE CA
International Classification:
H04L 27/01
H04L 7/02
H04L 7/00
H04L 7/02
H04L 7/00
US Classification:
375232, 375371, 375373
Abstract:
A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.
NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.