Jerry G Jex, Age 7010615 Tilley Rd S, Olympia, WA 98512

6384658, May 7, 2002

Sep 29, 2000

09/676313

Jerry G. Jex - Olympia WA

Intel Corporation - Santa Clara CA

H03K 3017

327295, 327171

An apparatus, method and means for providing a clock signal and an inverted clock signal having corresponding rise and fall edge rates, being resistant to load variations, process variations, voltage variations, and temperature variations. The apparatus output exceeds a threshold voltage for apparatus circuit paths. In one aspect of the invention, a combination of N channel and P channel devices, viewed as symmetrical P stacks and N stacks, are utilized. Low output impedance and high gain is provided for resistance to load variations.

6466074, Oct 15, 2002

Mar 30, 2001

09/820899

Kersi H. Vakil - Olympia WA
William N. Roy - Lacey WA
Jerry G. Jex - Olympia WA

Intel Corporation - Santa Clara CA

H03K 300

327295, 327256, 327257, 327259, 327293, 326 82, 326 85, 326 87

A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

6549031, Apr 15, 2003

Nov 13, 2001

10/002418

Jerry G. Jex - Olympia WA
Arnaud Forestier - Federal Way WA
Kersi Vakil - Olympia WA
Abhimanyu Kolla - Tacoma WA

Intel Corporation - Santa Clara CA

H03K 1716

326 30, 326 82, 333 32

Point-to-point AC impedance compensation calculates and matches AC impedance for integrated circuit input and output buffers, taking into consideration impedances of printed circuit boards, connectors, cards, cables, and/or other interfaces on a computer bus, upon computer system power-up or on demand during operation using no additional package pins or traces in the printed circuit board, connector, card, or cable.

7050507, May 23, 2006

Apr 22, 2002

10/128615

Kersi H. Vakil - Olympia WA, US
Jerry G. Jex - Olympia WA, US
Arnaud J. Forestier - Federal Way WA, US
Abhimanyu Kolla - Federal Way WA, US

Intel Corporation - Santa Clara CA

H04L 27/00
H04L 27/04
H04L 27/06

375259, 375295, 375316

A signaling apparatus and system may include a data transmitter capable of sending strobe and one or more data streams having edges displaced by time periods corresponding to coded values. Auto-negotiation to compensate for less expensive interconnections may be accomplished using various embodiments of the invention. The data transmitter may be coupled to a medium and a data receiver. An article, including a machine-accessible medium, may contain data capable of causing a machine to carry out a communication method, including transmitting strobe and data streams having edges displaced by time periods corresponding to coded values. A coded information signal may comprise one or more edges displaced in time from various strobe signal edges, the displacement corresponding to coded values.

7158594, Jan 2, 2007

Aug 21, 2002

10/225691

Jed D. Griffin - Forest Grove OR, US
Jerry G. Jex - Olympia WA, US
Brett A. Prince - Beaverton OR, US
Keith M. Self - Aloha OR, US

Intel Corporation - Santa Clara CA

H04L 7/00
H04L 25/49
H03K 5/22

375354, 375296, 327 63

In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

7224739, May 29, 2007

Aug 21, 2002

10/226074

Jed D. Griffin - Forest Grove OR, US
Jerry G. Jex - Olympia WA, US
Brett A. Prince - Beaverton OR, US
Keith M. Self - Aloha OR, US

Intel Corporation - Santa Clara CA

H04L 27/00
H04L 7/00
H04L 5/14
H04B 1/00

375259, 375295, 375354, 370202, 455 43

In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.

7305023, Dec 4, 2007

Jul 23, 2003

10/625944

Jed D. Griffin - Forest Grove OR, US
Jerry G Jex - Olympia WA, US
Arnaud J. Forestier - Irvine CA, US
Kersi H. Vakil - Olympia WA, US
Abhimanyu Kolla - Tacoma WA, US

Intel Corporation - Santa Clara CA

H04B 1/38
H04L 7/00

375219, 375354

In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.

7308025, Dec 11, 2007

Jul 23, 2003

10/625945

Jerry G. Jex - Olympia WA, US
Jed D. Griffin - Forest Grove OR, US
Arnaud J. Forestier - Federal Way WA, US
Kersi H. Vakil - Olympia WA, US
Abhimanyu Kolla - Tacoma WA, US

Intel Corporation - Santa Clara CA

H04B 1/38
H04L 7/06

375219, 375354, 375364

In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.